Rewritable single-bit-per-cell flash memory
View Patent ↗Subject matter disclosed herein relates to multilevel flash memory, and more particularly to a method of changing a logic level of a single-bit-per-cell flash memory device multiple times before an erase operation.
1. A method comprising:
storing a first logic level as a single logic bit in a multilevel flash memory cell by injecting a first quantity of electrical charge into a floating gate of said multilevel flash memory cell; and
changing said first logic level of the stored single logic bit to a second stored single bit logic level by injecting a second quantity of electrical charge into said floating gate of said multilevel flash memory cell, wherein said first logic level and said second logic level comprise two states of said single logic bit stored in said multilevel flash memory cell.
2. A method comprising:
storing a first logic level as a single logic bit in a multilevel flash memory cell by injecting a first quantity of electrical charge into a floating gate of said multilevel flash memory cell;
changing said single logic bit to a second logic level by injecting a second quantity of electrical charge into said floating gate of said multilevel flash memory cell; and
changing said single logic bit from said second logic level to said first logic level by injecting a third quantity of electrical charge into said floating gate of said multilevel flash memory cell.
3. The method of claim 2 , further comprising:
changing said single logic bit from said first logic level to said second logic level by injecting a fourth quantity of electrical charge into said floating gate of said multilevel flash memory cell.
4. The method of claim 3 , wherein a sum of said first, second, third, and fourth quantities of electrical charge is less than or equal to a maximum threshold voltage for said multilevel flash memory cell.
5. The method of claim 4 , further comprising:
erasing said multilevel flash memory cell to change a logic level of said single logic bit if said maximum threshold voltage is reached.
6. The method of claim 3 , wherein said multilevel flash memory cell comprises a portion of a NOR flash memory.
7. The method of claim 3 , wherein said multilevel flash memory cell comprises a portion of a NAND flash memory.
8. A multilevel flash memory device comprising:
a memory cell array including a multilevel flash memory cell adapted to store multiple bits;
a write controller adapted to inject an electrical charge into a floating gate of said multilevel flash memory cell to store a single logic bit; and
a read controller adapted to interpret an output of said multilevel flash memory cell as said single logic bit stored in said multilevel flash memory cell.
9. The multilevel flash memory device of claim 8 , wherein said write controller is further adapted to inject additional electrical charge into said floating gate of said multilevel flash memory cell to change a logic level of said single logic bit.
10. The multilevel flash memory device of claim 8 , wherein said read controller is further adapted to interpret two or more different output levels of said multilevel flash memory cell as a same logic level of said single logic bit.
11. The multilevel flash memory device of claim 8 , wherein said write controller is further adapted to change a logic level of said single logic bit one or more times without erasing said multilevel flash memory cell.
12. The multilevel flash memory device of claim 11 , wherein said write controller is further adapted to erase said memory cell array to further change said logic level of said single logic bit after changing said logic level said one or more times.
13. The multilevel flash memory device of claim 8 , wherein said memory cell array comprises a portion of a NOR flash memory.
14. The multilevel flash memory device of claim 8 , wherein said memory cell array comprises a portion of a NAND flash memory.
15. An apparatus comprising:
means for storing a first logic level as a single logic bit in a multilevel flash memory cell by injecting a first quantity of electrical charge into a floating gate of said multilevel flash memory cell; and
means for changing said first logic level of the stored single logic bit to a second stored single bit logic level by injecting a second quantity of electrical charge into said floating gate of said multilevel flash memory cell, wherein said first logic level and said second logic level comprise two states of said single logic bit stored in said multilevel flash memory cell.
16. The apparatus of claim 15 , wherein said multilevel flash memory cell comprises a portion of a NOR flash memory.
17. An apparatus comprising:
means for storing a first logic level as a single logic bit in a multilevel flash memory cell by injecting a first quantity of electrical charge into a floating gate of said multilevel flash memory cell;
means for changing said single logic bit to a second logic level by injecting a second quantity of electrical charge into said floating gate of said multilevel flash memory cell; and
means for changing said single logic bit from said second logic level to said first logic level by injecting a third quantity of electrical charge into said floating gate of said multilevel flash memory cell.
18. The apparatus of claim 17 , further comprising:
means for changing said single logic bit from said first logic level to said second logic level by injecting a fourth quantity of electrical charge into said floating gate of said multilevel flash memory cell.
19. The apparatus of claim 18 , wherein a sum of said first, second, third, and fourth quantities of electrical charge is less than or equal to a maximum threshold voltage for said multilevel flash memory cell.
20. The apparatus of claim 19 , further comprising:
means for erasing said multilevel flash memory cell to change a logic level of said single logic bit if said maximum threshold voltage is reached.