Configurable partitions for non-volatile memory
View Patent ↗Example embodiments for configuring a non-volatile memory device may comprise configuring M physical partitions of the non-volatile memory into two or more banks, wherein the two or more banks respectively comprise one or more of the M physical partitions, and wherein at least a first of the M physical partitions comprises a first size and wherein at least a second of the M physical partitions comprises a second size.
1. A method, comprising:
receiving one or more signals representative of a bank configuration value at a non-volatile memory device comprising M physical partitions;
configuring the non-volatile memory device into two or more banks at least in part in response to receiving said one or more signals representative of the bank configuration value, wherein one or more of the two or more banks respectively comprise two or more of the M physical partitions individually comprising different storage capacities; and
remapping N logical partitions to the M physical partitions, wherein N is greater than M, and wherein M and N individually comprise positive integers.
2. The method of claim 1 , further comprising:
receiving one or more signals representative of a memory access request to a first of the N logical partitions; and
translating the received memory access request to the first of the N logical partitions to a memory access request to one of the M physical partitions according to said remapping.
3. The method of claim 2 , further comprising:
storing said one or more signals representative of the bank configuration value in a bank configuration register in the non-volatile memory, wherein said configuring the non-volatile memory comprises configuring the non-volatile memory at least in part in response to said storing the one or more signals representative of the bank configuration value in the bank configuration register, wherein said two or more banks are configured in accordance with the bank configuration value.
4. The method of claim 3 , wherein said two or more banks comprise a first bank and a second bank, and wherein said bank configuration value defines a boundary between the first bank and the second bank.
5. The method of claim 2 , wherein said M physical partitions comprise 1+log 2 (N) physical partitions, wherein N comprises a positive integer that is a power of two.
6. The method of claim 5 , wherein N is sixteen and wherein M is five, wherein a first of the M physical partitions comprises a storage capacity of T/2, wherein T comprises a total storage capacity of the non-volatile memory, wherein a second of the M physical partitions comprises a storage capacity of T/4, wherein a third of the M physical partitions comprises a storage capacity of T/8, wherein a fourth of the M physical partitions comprises a storage capacity of T/16, and wherein a fifth of the M physical partitions comprises a storage capacity of T/16.
7. The method of claim 5 , wherein N is eight and wherein M is four, wherein a first of the M physical partitions comprises a storage capacity of T/2, wherein T comprises a total storage capacity of the non-volatile memory, wherein a second of the M physical partitions comprises a storage capacity of T/4, wherein a third of the M physical partitions comprises a storage capacity of T/8, and wherein a fourth of the M physical partitions comprises a storage capacity of T/8.
8. A non-volatile memory device, comprising:
M physical partitions configured into two or more banks, wherein one or more of the two or more banks respectively comprise two or more of the M physical partitions individually comprising different storage capacities; and
partition remapping logic to remap N logical partitions to the M physical partitions, wherein N is greater than M, and wherein M and N individually comprise positive integers.
9. The memory device of claim 8 , further comprising:
a plurality of input buffers to receive address and control signals, said input buffers to receive a memory access request to a first of the N logical partitions, said partition remapping logic to translate the received memory access request to the first of the N logical partitions to a memory access request to one of the M physical partitions according to said remapping.
10. The memory device of claim 9 , further comprising:
a bank configuration register to store a bank configuration value received at the input buffers, wherein said two or more banks are configured in accordance with the bank configuration value at least in part in response to said storing the bank configuration value in the bank configuration register.
11. The memory device of claim 10 , wherein said two or more banks comprise a first bank and a second bank, and wherein said bank configuration value defines a boundary between the first bank and the second bank.
12. The memory device of claim 9 , wherein the M physical partitions comprise 1+log 2 (N) physical partitions, wherein N comprises a positive integer that is a power of two.
13. The memory device of claim 12 , wherein N is sixteen and wherein M is five, wherein a first of the M physical partitions comprises a storage capacity of T/2, wherein T comprises a total storage capacity of the non-volatile memory, wherein a second of the M physical partitions comprises a storage capacity of T/4, wherein a third of the M physical partitions comprises a storage capacity of T/8, wherein a fourth of the M physical partitions comprises a storage capacity of T/16, and wherein a fifth of the M physical partitions comprises a storage capacity of T/16.
14. The memory device of claim 12 , wherein N is eight and wherein M is four, wherein a first of the M physical partitions comprises a storage capacity of T/2, wherein T comprises a total storage capacity of the non-volatile memory, wherein a second of the M physical partitions comprises a storage capacity of T/4, wherein a third of the M physical partitions comprises a storage capacity of T/8, and wherein a fourth of the M physical partitions comprises a storage capacity of T/8.
15. A system, comprising:
a processor; and
a non-volatile memory device coupled to the processor, the memory device comprising
M physical partitions configured into two or more banks, wherein one or more of the two or more banks respectively comprise two or more of the M physical partitions individually comprising different storage capacities; and
partition remapping logic to remap N logical partitions to M physical partitions, wherein N is greater than M, and wherein M and N individually comprise positive integers.
16. The system of claim 15 , wherein the memory device further comprises a plurality of input buffers to receive address and control signals from the processor, said input buffers to receive a memory access request from the processor to a first of the N logical partitions, said partition remapping logic to translate the received memory access request to the first of the N logical partitions to a memory access request to one of the M physical partitions according to said remapping.
17. The system of claim 16 , wherein the memory device further comprises a bank configuration register to store a bank configuration value received at the input buffers from the processor, wherein said two or more banks are configured in accordance with the bank configuration value at least in part in response to said storing the bank configuration value in the bank configuration register, wherein said bank configuration value defines a boundary between a first bank and a second bank of said two or more banks.
18. The system of claim 16 , wherein said M physical partitions comprise 1+log 2(N) physical partitions, wherein N comprises a positive integer that is a power of two.
19. The system of claim 18 , wherein N is sixteen and wherein M is five, and wherein a first of the M physical partitions comprises a storage capacity of T/2, wherein T comprises a total storage capacity of the non-volatile memory, wherein a second of the M physical partitions comprises a storage capacity of T/4, wherein a third of the M physical partitions comprises a storage capacity of T/8, wherein a fourth of the M physical partitions comprises a storage capacity of T/16, and wherein a fifth of the M physical partitions comprises a storage capacity of T/16.
20. The system of claim 18 , wherein N is eight and wherein M is four, and wherein a first of the M physical partitions comprises a storage capacity of T/2, wherein T comprises a total storage capacity of the non-volatile memory, wherein a second of the M physical partitions comprises a storage capacity of T/4, wherein a third of the M physical partitions comprises a storage capacity of T/8, and wherein a fourth of the M physical partitions comprises a storage capacity of T/8.