Granted Patent B2

US 9,037,788 · App. 12/895,627 · Granted May 19, 2015

Abstract

Claims (33)

1. A method comprising:

A. rebooting a processor that is configured to access a persistent main memory in response to an occurrence of a disruptive event experienced by said processor, said persistent main memory comprising volatile and nonvolatile memory;

B. determining validity of a base table maintained in the persistent main memory with a memory controller, wherein if the base table is invalid, the processor is rebooted so that the base table is reloaded from an external drive, and wherein if the base table is valid proceed to step C;

C. validating an individual page referenced by the validated base page table by the memory controller, wherein if the individual page is not valid, reload the individual page from the external drive and proceed to step E, and wherein if the individual page is valid proceed to step D;

D. re-using valid individual page information; and

E. repeating step C until every individual page in the validated base page table is validated.

2. The method of claim 1 , wherein invalidity of said base table or individual page results from a process of said processor that is disrupted by said disruptive event.

3. The method of claim 1 , further comprising storing said individual page in said persistent main memory.

4. The method of claim 1 , wherein said persistent memory comprises phase change memory (PCM).

5. The method of claim 1 , further comprising setting or resetting a flag to indicate that said nonvolatile memory was being written during a disruptive event.

6. The method of claim 5 , wherein the disruptive event is a power loss.

7. A memory device comprising:

circuitry to re-initialize a processor that is configured to access a persistent main memory subsequent to a disruptive event experienced by said processor, said persistent main memory comprising volatile and nonvolatile memory, wherein said circuitry is configured to:

A. retrieve a base table maintained in said persistent main memory and determine validity of said base table wherein if the base table is invalid, the circuitry is configured to reboot the processor so that the base table is reloaded from an external drive, and wherein if the base table is valid, the circuitry is configured to proceed to step B;

B. validate an individual page referenced by the validated base page table by the memory controller, wherein if the individual pages is not valid, reload the individual page from the external drive and proceed to step D, and wherein if the individual page is valid proceed to step C;

C. re-use valid individual page information; and

D. repeat step B until every individual page in the validated base page table is validated.

8. The memory device of claim 7 , wherein said base table and individual page comprise memory contents resulting from processes executed prior to said disruptive event.

9. The memory device of claim 8 , wherein said base table and individual page comprise a parity value of said memory contents, said parity value determined prior to said disruptive event.

10. The memory device of claim 9 , wherein said circuitry is further adapted to determine a parity value of said memory contents subsequent to said disruptive event, and wherein said validity is based, at least in part, on a comparison of said parity value determined prior to said disruptive event with said parity value determined subsequent to said disruptive event.

11. The memory device of claim 7 , wherein invalidity of said base table or individual page results from a process of said processor that is disrupted by said disruptive event.

12. The memory device of claim 7 , wherein said persistent main memory comprises phase change memory (PCM).

13. The memory device of claim 7 , further comprising a memory controller configured to set or reset a flag to indicate that said nonvolatile memory was being written during a disruptive event.

14. A system comprising:

a processor to host one or more applications, the processor configured to access a persistent main memory; and

a memory device comprising:

circuitry having at least a first interface to said persistent main memory comprising volatile and nonvolatile memory and at least a second interface to said processor, wherein said circuitry is configured to:

A. retrieve a base table maintained in said persistent main memory and determine validity of said base table, wherein if the base table is invalid, the circuitry is configured to reboot the processor so that the base table is reloaded from an external drive, and wherein if the base table is valid, the circuitry is configured to proceed to step B;

B. validate an individual page referenced by the validated base page table by the memory controller, wherein if the individual pages is not valid, reload the individual page from the external drive and proceed to step D, and wherein if the individual page is valid proceed to step C;

C. re-use valid individual page information; and

D. repeat step B until every individual page in the validated base page table is validated.

15. The system of claim 14 , further comprising a hypervisor to provide a virtual environment.

16. The system of claim 14 , further comprising a memory controller configured to set or reset a flag to indicate that said nonvolatile memory was being written during a disruptive event.

Assignments (8)