Reading memory cell history during program operation for adaptive programming
View Patent ↗Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a memory device.
1. A method comprising:
maintaining use-history information regarding a memory array in a first portion of memory cells in said memory array;
reading said first portion of memory cells during a program-verify process to program a second portion of memory cells, wherein said first portion of memory cells and said second portion of memory cells are responsive to a particular wordline; and
modifying parameters of said program-verify process based, at least in part, on read use-history information.
2. The method of claim 1 , wherein said program-verify process comprises an incremental step pulse programming (ISPP) process, wherein a plurality of program pulses alternate with a plurality of verify processes.
3. The method of claim 2 , wherein said parameters of said program-verify process comprise program pulse amplitude, program pulse width, program pulse slope, program pulse shape, and/or program pulse step size.
4. The method of claim 1 , wherein said use-history information comprises a count of erase cycles experienced by said second portion of memory cells, a count of program-verify cycles experienced by said second portion of memory cells, a count of erase pulses in a last erase operation, or a duration of said last erase operation.
5. The method of claim 1 , further comprising:
updating said use-history information in response to a process of erasing said second portion of memory cells.
6. The method of claim 1 , further comprising:
programming said first portion of memory cells to a higher programming threshold voltage than that of said second portion of memory cells in a programmed state.
7. The method of claim 1 , wherein said memory array comprises a NAND block array.
8. An apparatus comprising:
a controller to:
store use-history information in a first portion of memory cells in a memory array, wherein said use-history information regards said memory array;
read said first portion of memory cells during a program-verify process to program a second portion of memory cells, wherein said first portion of memory cells and said second portion of memory cells are responsive to a particular wordline; and
modify said program-verify process based, at least in part, on read said use-history information.
9. The apparatus of claim 8 , wherein said program-verify process comprises an incremental step pulse programming (ISPP) process.
10. The apparatus of claim 9 , wherein modifying said program-verify process comprises modifying program pulse amplitude, program pulse width, and/or program pulse step size of said program-verify process.
11. The apparatus of claim 8 , wherein said use-history information comprises a count of erase cycles experienced by said second portion of memory cells.
12. The apparatus of claim 8 , said controller to update said use-history information in response to a process of erasing said second portion of memory cells.
13. The apparatus of claim 8 , said controller to program said first portion of memory cells to a higher threshold voltage amplitude than that of said second portion of memory cells in a programmed state.
14. The apparatus of claim 8 , wherein said memory array comprises a NAND array.
15. A system comprising:
a memory device comprising a memory array, said memory device further comprising a memory controller to:
maintain use-history information regarding said memory array in a first portion of memory cells in said memory array;
read said first portion of memory cells during a program-verify process to program a second portion of memory cells, wherein said first portion of memory cells and said second portion of memory cells are responsive to a particular wordline; and
modify parameters of said program-verify process based, at least in part, on read said use-history information; and
a processor to host one or more applications and to initiate a write command to said memory controller to program said second portion of memory cells in said memory array.
16. The system of claim 15 , wherein said program-verify process comprises a plurality of program pulses that alternate with a plurality of verify processes.
17. The system of claim 16 , wherein said parameters of said program-verify process comprise program pulse amplitude, program pulse width, or program pulse step size.
18. The system of claim 15 , wherein said use-history information comprises a count of erase cycles experienced by said second portion of memory cells or a count of program-verify cycles experienced by said second portion of memory cells.
19. The system of claim 15 , said controller to program said first portion of memory cells to a threshold voltage higher than that of said second portion of memory cells in a programmed state.
20. The system of claim 15 , wherein said memory array comprises NAND memory cells.
21. The apparatus of claim 8 , wherein modifying said program-verify process comprises modifying at least one of a program pulse width, a program pulse slope, a program pulse shape, and a program pulse step size of said program-verify process.
22. The apparatus of claim 8 , wherein said use-history information comprises at least one of a count of program-verify cycles experienced by said second portion of memory cells, a count of erase pulses in a last erase operation, and a duration of said last erase operation.