Solid state drive controller
View Patent ↗A memory device may comprise circuitry to adjust between latency and throughput in transferring information through a memory port, wherein the circuitry may be capable of configuring individual partitions or individual sectors as high-throughput storage or low-latency storage.
1. An apparatus, comprising:
a memory port for coupling to a non-volatile memory array, said non-volatile memory array being hierarchically organized in partitions and sectors; and
circuitry to adjust between latency and throughput in transferring information through the memory port, wherein said circuitry is capable of configuring individual said partitions or individual said sectors as high-throughput storage or low-latency storage;
wherein said circuitry is configured to:
determine whether a received request is a configuration request or a request other than a configuration request;
responsive to determining that the received request is a request other than a configuration request, service the received request;
responsive to determining that the received request is a configuration request:
configure at least one of the said partitions or the said sectors associated with the configuration request as high-throughput or low-latency according to the configuration request; and
update a configuration table according to the received configuration request.
2. The apparatus of claim 1 wherein the memory port comprises a plurality of channels for accessing the memory array, and wherein said circuitry is capable of distributing said information to one or more of the channels, increasing a number of channels to reduce said latency, or reducing a number of channels to increase said throughput.
3. The apparatus of claim 2 , wherein said circuitry comprises circuitry to distribute requests to either a greater or lesser number of said channels on a partition-by-partition basis.
4. The apparatus of claim 2 , wherein said circuitry comprises circuitry to distribute requests to either a greater or lesser number of said channels on a sector-by-sector basis.
5. The apparatus of claim 2 , wherein said circuitry comprises circuitry to store configuration information for said non-volatile memory array.
6. A method, comprising:
configuring individual partitions or individual sectors of a non-volatile memory array as high-throughput storage or low-latency storage;
transferring information stored in said individual partitions or said individual sectors through a memory port of a memory controller; and
adjusting between latency and throughput for said transferring information based, at least in part, on said configuring;
wherein said configuring comprises:
determining whether a received request is a configuration request or a request other than a configuration request;
responsive to determining that the received request is a request other than a configuration request, servicing the received request;
responsive to determining that the received request is a configuration request:
configuring at least one of the said individual partitions or the said individual sectors associated with the configuration request as high-throughput or low-latency according to the configuration request; and
updating a configuration table according to the received configuration request.
7. The method of claim 6 , wherein the memory port comprises a plurality of channels to access said non-volatile memory array and, wherein the method further comprises selectively increasing the number of said channels to which said information is distributed to reduce said latency or decreasing the number of said channels to which said information is distributed to increase said throughput.
8. The method of claim 7 , and further comprising distributing said information to an increased number of said channels or a decreased number of said channels on a drive-wide basis.
9. The method of claim 7 , and further comprising distributing said information to an increased number of said channels or a decreased number of said channels on a partition-by-partition basis.
10. The method of claim 7 , and further comprising distributing said information to an increased number of said channels or a decreased number of said channels on a sector-by-sector basis.
11. The method of claim 7 , and further comprising storing configuration information indicative of low-latency regions within said non-volatile memory array.
12. The method of claim 7 , and further comprising storing configuration information indicative of high-throughput regions within said non-volatile memory array.
13. The method of claim 7 and further comprising receiving user input selection through an application from a host.
14. The method of claim 7 and further comprising receiving user input selection through a driver from a host.
15. An apparatus comprising:
a non-volatile memory array accessible through a memory port, said non-volatile memory array being hierarchically organized in partitions and sectors; and
a memory controller comprising circuitry to adjust between latency and throughput in transferring information through said memory port, wherein said circuitry is capable of configuring individual said partitions or individual said sectors as high throughput storage or low-latency storage; and
wherein said circuitry is further configured to:
determine whether a received request is a configuration request or a request other than a configuration request;
responsive to determining that the received request is a request other than a configuration request, service the received request;
responsive to determining that the received request is a configuration request:
configure at least one of the said partitions or the said sectors associated with the configuration request as high-throughput or low-latency according to the configuration request; and
update a configuration table according to the received configuration request.
16. The apparatus of claim 15 , wherein the non-volatile memory array and memory controller comprise a solid state drive (SSD).
17. The apparatus of claim 16 wherein said circuitry is capable of storing configuration information for the non-volatile memory array.
18. The apparatus of claim 15 further comprising a processor hosting applications to initiate memory requests to access said non-volatile memory array through said memory controller.
19. The apparatus of claim 18 wherein said applications are capable of providing a user input selection.