Forming resistive random access memories together with fuse arrays
View Patent ↗A resistive random access memory array may be formed on the same substrate with a fuse array. The random access memory and the fuse array may use the same active material. For example, both the fuse array and the memory array may use a chalcogenide material as the active switching material. The main array may use a pattern of perpendicular sets of trench isolations and the fuse array may only use one set of parallel trench isolations. As a result, the fuse array may have a conductive line extending continuously between adjacent trench isolations. In some embodiments, this continuous line may reduce the resistance of the conductive path through the fuses.
1. A method comprising:
forming a chalcogenide memory array using a first set of steps including forming select devices by forming two sets of orthogonal trenches; and
forming a fuse array at the same time on the same substrate using the first set of steps including only forming one set of said trenches in the fuse array to form conductive lines.
2. The method of claim 1 including forming address lines transverse to said conductive lines, said address lines including only one fuse per line.
3. The method of claim 2 including forming interrupted address lines wherein said address lines include a gap, each address line including a first portion on one side of said gap and a second portion on the opposite side of the said gap.
4. The method of claim 3 including forming fuses only on one of said first or second portions of said address lines.
5. The method of claim 4 including forming fuses at the intersection of an address line and a conductive line and forming some of said address line portions to be shorter than others so that some of said address line portions do not overlap a conductive line.
6. A method comprising:
forming a chalcogenide memory array with a first set of parallel trenches and a second set of parallel trenches perpendicular to said first set of parallel trenches; and
forming a fuse array on the same substrate with said chalcogenide memory array and forming said first set of parallel trenches to extend into said fuse array.
7. The method of claim 6 including forming address lines including only one fuse per line.
8. The method of claim 7 including forming interrupted address lines wherein said address lines include a gap, each address line including a first portion on one side of said gap and a second portion on the opposite side of said gap.
9. The method of claim 8 including forming fuses only on one of said first or second portions of said address lines.
10. The method of claim 9 including forming fuses at an intersection of an address line and a conductive line and forming some of said address line portions shorter than others of said address lines so that some of said address line portions do not overlap a conductive line.
11. An integrated circuit comprising:
a semiconductor substrate;
a chalcogenide memory array formed on said substrate, said chalcogenide memory array including a first set of parallel trenches and a second set of parallel trenches perpendicular to said first set of parallel trenches; and
a fuse array on said substrate, said first set of parallel trenches extending into said fuse array.
12. The circuit of claim 11 , said fuse array including address lines and including only one fuse per address line.
13. The circuit of claim 12 including said address lines including gaps where said address lines include a first portion on one side of said gap and a second portion on the opposite side of said gap.
14. The circuit of claim 13 including said fuses only being positioned on one of said first or second portions of said address lines.
15. The circuit of claim 14 wherein said fuses are formed at the intersection of an address line and a conductive line and some of said address line portions being shorter than others so that some of said address line portions do not overlap a conductive line.
16. The circuit of claim 14 wherein said circuit is a phase change memory.