Error detection or correction of a portion of a codeword in a memory device
View Patent ↗Example embodiments described herein may relate error detection and correction on a portion of a codeword in a memory device.
1. A method of retrieving data, the method comprising:
performing an error detection operation on a sub-codeword of a plurality of sub-codewords of a codeword stored in a memory array at least in part in response to a read access request;
performing an error detection and correction operation on the codeword at least in part in response to a detection of an error for the sub-codeword to generate a corrected sub-codeword;
receiving a program command to write incoming information to a storage location in the memory array of a second sub-codeword of the plurality of sub-codewords;
reading the second sub-codeword and said one or more parity bits, wherein said second sub-codeword comprises one or more data bits and one or more cyclic redundancy check bits;
generating new cyclic redundancy check bits for the second sub-codeword based at least in part on the incoming information;
generating one or more new parity bits for the codeword based at least in part on the previous one or more parity bits and on the incoming information; and
writing the incoming information and the new cyclic redundancy check bits to the storage location in the memory array of the second sub-codeword, and replacing the previous one or more parity bits with the new one or more parity bits.
2. The method of claim 1 ,
wherein the error detection operation is performed without accessing the whole of the codeword.
3. The method of claim 1 , further comprising providing the sub-codeword to an input/output interface at least in part in response to a non-detection of an error for the sub-codeword.
4. The method of claim 1 , further comprising providing the corrected sub-codeword to an input/output interface to satisfy the read access request.
5. The method of claim 1 , wherein said performing the error detection and correction operation comprises waiting until the entire codeword is available for reading prior to performing the error detection and correction operation on the codeword.
6. The method of claim 5 , wherein said performing the error detection operation on the sub-codeword comprises performing a cyclic redundancy check of the sub-codeword, wherein the sub-codeword comprises one or more data bits and one or more cyclic redundancy check bits.
7. The method of claim 6 , wherein said codeword further comprises one or more parity bits, and wherein said performing said error detection and correction operation on the codeword comprises basing said error detection and correction at least in part on respective states of said one or more parity bits.
8. A memory device, comprising:
a memory array configured to store a codeword comprising one or more sub-codewords; and
a controller configured to perform an error detection operation on a sub-codeword of the one or more sub-codewords at least in part in response to a read access request, the controller further configured to:
perform an error detection and correction operation on the codeword at least in part in response to a detection of an error for the sub-codeword to generate a corrected sub-codeword;
write incoming information received at the input/output interface to a storage location in the memory array of a second sub-codeword of the plurality of sub-codewords at least in part in response to a program command;
read the second sub-codeword and said one or more parity bits, wherein said second sub-codeword comprises one or more data bits and one or more cyclic redundancy check bits;
generate new cyclic redundancy check bits for the second sub-codeword based at least in part on the incoming information;
generate one or more new parity bits for the codeword based at least in part on the previous one or more parity bits and on the incoming information;
write the incoming information and the new cyclic redundancy check bits to the storage location in the memory array for the second sub-codeword; and
replace the previous one or more parity bits with the new one or more parity bits.
9. The memory device of claim 8 ,
wherein the error detection operation is performed without accessing the whole of the codeword.
10. The memory device of claim 8 , further comprising an input/output interface to transmit the corrected sub-codeword to fulfill the read access request.
11. The memory device of claim 8 , the controller to perform the error detection and correction operation at least in part by waiting until the entire codeword is available for reading prior to performing the error detection and correction operation on the codeword.
12. The memory device of claim 11 , the controller further to perform the error detection operation on the sub-codeword at least in part by performing a cyclic redundancy check of the sub-codeword, wherein the sub-codeword comprises one or more data bits and one or more cyclic redundancy check bits.
13. The memory device of claim 12 , wherein said codeword further comprises one or more parity bits, the controller further to perform said error detection and correction operation on the codeword by basing said error detection and correction at least in part on respective states of said one or more parity bits.
14. A system, comprising:
a master controller; and
one or more non-volatile memory devices coupled to the master controller, wherein the one or more non-volatile memory devices individually comprise:
a memory array configured to store a codeword comprising one or more sub-codewords; and
a local controller configured to perform an error detection operation on a sub-codeword of the one or more sub-codewords at least in part in response to a read access request, the local controller further configured to:
perform an error detection and correction operation on the codeword at least in part in response to a detection of an error for the sub-codeword to generate a corrected sub-codeword;
write incoming information received at the input/output interface to a storage location in the memory array of a second sub-codeword of the plurality of sub-codewords at least in part in response to a program command;
read the second sub-codeword and said one or more parity bits, wherein said second sub-codeword comprises one or more data bits and one or more cyclic redundancy check bits;
generate new cyclic redundancy check bits for the second sub-codeword based at least in part on the incoming information;
generate one or more new parity bits for the codeword based at least in part on the previous one or more parity bits and on the incoming information;
write the incoming information and the new cyclic redundancy check bits to the storage location in the memory array for the second sub-codeword; and
replace the previous one or more parity bits with the new one or more parity bits.
15. The system of claim 14 ,
wherein the error detection operation is performed without accessing the whole of the codeword.
16. The system of claim 14 , said one or more of the plurality of non-volatile memory devices individually further comprising an input/output interface to transmit the corrected sub-codeword to the master controller to fulfill the read access request.
17. The system of claim 14 , the local controller to perform the error detection and correction operation at least in part by waiting until the entire codeword is available for reading prior to performing the error detection and correction operation on the codeword.
18. The system of claim 17 , the local controller further to perform the error detection operation on the sub-codeword at least in part by performing a cyclic redundancy check of the sub-codeword, wherein the sub-codeword comprises one or more data bits and one or more cyclic redundancy check bits.
19. The system of claim 18 , wherein said codeword further comprises one or more parity bits, the local controller further to perform said error detection and correction operation on the codeword by basing said error detection and correction at least in part on respective states of said one or more parity bits.
20. The system of claim 14 , wherein the system comprises a solid state drive.