IP Library Granted Patent US 8,078,796
Granted Patent B2
US 8,078,796 · App. 12/423,226 · Granted Dec 13, 2011

Method for writing to and erasing a non-volatile memory

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,078,796
App. No.
12/423,226
Granted
Dec 13, 2011
Kind
B2
Abstract

A method for writing to and erasing a non-volatile memory is described. The method includes determining the size of a command window for use in n write operations for the non-volatile memory, each write operation having the same time period. A long latency erase command is sliced by a factor of n to provide a plurality of erase slices, each erase slice having the same time period. The method further includes executing n commands to the non-volatile memory, each command composed of the combination of one of the n write operations and one of the erase slices. The total of the time period of one erase slice added to the time period of one write operation is less than or equal to the size of the command window.

Claims (29)

1. A computer-implemented method for writing to and erasing a non-volatile memory, the method comprising:

determining the size of a command window for use in n write operations for the non-volatile memory, each write operation having the same time period;

slicing a long latency erase command by a factor of n to provide a plurality of erase slices, each erase slice having the same time period; and

executing n commands to the non-volatile memory, each command comprised of the combination of one of the n write operations and one of the erase slices, wherein the total of the time period of one erase slice added to the time period of one write operation is less than or equal to the size of the command window.

2. The computer-implemented method of claim 1 , wherein the total of the time period of one erase slice added to the time period of one write operation is less than the size of the command window.

3. The computer-implemented method of claim 1 , wherein the non-volatile memory is a NOR flash memory.

4. The computer-implemented method of claim 1 , wherein n is equal to 10, the size of the command window is approximately 72 milliseconds, the time period of one erase slice is approximately 70 milliseconds, and the time period of one write operation is approximately 2 milliseconds.

5. A computer-implemented method for writing to and erasing a non-volatile memory, the method comprising:

dynamically determining the size of a command window for use in n write operations for the non-volatile memory, each write operation having the same time period, the dynamically determining based on a dynamic latency erase command;

slicing the dynamic long latency erase command by a factor of n to provide a plurality of erase slices, each erase slice having the same time period, the dynamic long latency erase command based on an actual state of the non-volatile memory; and

executing n commands to the non-volatile memory, each command comprised of the combination of one of the n write operations and one of the erase slices, wherein the total of the time period of one erase slice added to the time period of one write operation is less than or equal to the size of the command window.

6. The computer-implemented method of claim 5 , wherein the total of the time period of one erase slice added to the time period of one write operation is less than the size of the command window.

7. The computer-implemented method of claim 5 , wherein the non-volatile memory is a NOR flash memory.

8. The computer-implemented method of claim 5 , wherein n is equal to 10, the size of the command window is approximately 52 milliseconds, the time period of one erase slice is approximately 50 milliseconds, and the time period of one write operation is approximately 2 milliseconds.

9. The computer-implemented method of claim 5 , wherein n is equal to 10, the size of the command window is approximately 152 milliseconds, the time period of one erase slice is approximately 150 milliseconds, and the time period of one write operation is approximately 2 milliseconds.

10. The computer-implemented method of claim 5 , wherein the actual state of the non-volatile memory comprises a small erase backlog, and wherein the dynamic latency erase command is approximately 500 milliseconds.

11. The computer-implemented method of claim 5 , wherein the actual state of the non-volatile memory comprises a large erase backlog, and wherein the dynamic latency erase command is approximately 1500 milliseconds.

12. A machine-accessible storage medium having instructions stored thereon which cause a data processing system to perform a method for writing to and erasing a non-volatile memory, the method comprising:

determining the size of a command window for use in n write operations for the non-volatile memory, each write operation having the same time period;

slicing a long latency erase command by a factor of n to provide a plurality of erase slices, each erase slice having the same time period; and

executing n commands to the non-volatile memory, each command comprised of the combination of one of the n write operations and one of the erase slices, wherein the total of the time period of one erase slice added to the time period of one write operation is less than or equal to the size of the command window.

13. The machine-accessible storage medium of claim 12 , wherein the total of the time period of one erase slice added to the time period of one write operation is less than the size of the command window.

14. The machine-accessible storage medium of claim 12 , wherein the non-volatile memory is a NOR flash memory.

15. The machine-accessible storage medium of claim 12 , wherein n is equal to 10, the size of the command window is approximately 72 milliseconds, the time period of one erase slice is approximately 70 milliseconds, and the time period of one write operation is approximately 2 milliseconds.

16. The machine-accessible storage medium of claim 12 , wherein determining the size of the command window is performed dynamically and is based on a dynamic latency erase command, wherein slicing the long latency erase command comprises slicing the dynamic long latency erase command, the dynamic long latency erase command based on an actual state of the non-volatile memory.

17. The machine-accessible storage medium of claim 16 , wherein the total of the time period of one erase slice added to the time period of one write operation is less than the size of the command window.

18. The machine-accessible storage medium of claim 16 , wherein the non-volatile memory is a NOR flash memory.

19. The machine-accessible storage medium of claim 16 , wherein n is equal to 10, the size of the command window is approximately 52 milliseconds, the time period of one erase slice is approximately 50 milliseconds, and the time period of one write operation is approximately 2 milliseconds.

20. The machine-accessible storage medium of claim 16 , wherein n is equal to 10, the size of the command window is approximately 152 milliseconds, the time period of one erase slice is approximately 150 milliseconds, and the time period of one write operation is approximately 2 milliseconds.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 26, 2011
From: NUMONYX B.V.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 027126/0176 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 10, 2011
From: NUMONYX B. V.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 027046/0040 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2010
From: RUDELIC, JOHN
To: NUMONYX B.V.
Reel/Frame 024682/0523 →