IP Library Granted Patent US 8,530,874
Granted Patent B1
US 8,530,874 · App. 12/828,463 · Granted Sep 10, 2013

Insulated phase change memory

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Quick Facts
Patent No.
US 8,530,874
App. No.
12/828,463
Granted
Sep 10, 2013
Kind
B1
Abstract

A phase change memory may include a plurality of thin layers covering a stack including a chalcogenide and a heater. The thin layers may form a barrier to heat loss. The thin layers may be the same or different materials. The layers may also be chemically or morphologically altered to improve the adverse affect of the interface between the layers on heat transfer.

Claims (30)

1. A phase change memory comprising:

a chalcogenide;

a heater positioned to heat the chalcogenide; and

an electrode in electrical contact with the chalcogenide, wherein the heater, chalcogenide, and electrode form a stack; and

an interfacial insulator encasing said stack, wherein the interfacial insulator includes a first dielectric layer encasing the chalcogenide, the heater, and the electrode, and a second dielectric layer encasing the first dielectric layer, the chalcogenide, the heater, and the electrode, wherein the first dielectric layer comprises at least one of a chemically altered surface or a morphologically altered surface in contact with the second dielectric layer.

2. The memory of claim 1 wherein said first and second dielectric layers are less than 20 Angstroms thick.

3. The memory of claim 2 wherein said dielectric layers are different materials.

4. The memory of claim 1 wherein said interfacial insulator covers the stack on three sides.

5. A method comprising:

forming an interfacial insulator around a stack including a chalcogenide material, a heater, and an electrode, wherein the interfacial insulator comprises a first dielectric layer encasing the stack and a second dielectric layer encasing the first dielectric layer, wherein forming the interfacial insulator comprises altering a surface of the first dielectric layer.

6. The method of claim 5 including said dielectric layers have a thickness less than 20 nanometers and are in face-to-face contact with one another.

7. The method of claim 6 including forming said dielectric layers of different materials.

8. The method of claim 5 , wherein altering the surface of the first dielectric layer comprises morphologically altering the surface of the first dielectric layer.

9. The method of claim 5 , wherein altering the surface of the first dielectric layer comprises chemically altering the surface of the first dielectric layer.

10. The method of claim 5 wherein said forming the interfacial insulator comprises covering said stack on three sides with said interfacial insulator.

11. A phase change memory comprising:

at least two memory cells, a memory cell of the at least two memory cells including a chalcogenide material, a heater, and an electrode; and

interfacial insulators encasing respective memory cells of the at lest two memory cells, an interfacial insulator of the interfacial insulators comprising a first dielectric layer encasing the respective memory cells and a second dielectric layer encasing the first dielectric layer and the respective memory cells, wherein the first dielectric layer comprises at least one of a chemically altered surface or a morphologically altered surface in contact with the second dielectric later.

12. The memory of claim 11 wherein said encasing comprises covering said cell on at least three sides.

13. A phase change memory comprising:

at least two memory cells, a memory cell of the at least two memory cells including a chalcogenide material, a heater in electrical contact with the chalcogenide material, and an electrode, wherein the memory cell has a cell size of less than 50 nanometers; and

interfacial insulators encasing respective memory cells of the at least two memory cells, an interfacial insulator of the interfacial insulators comprising a first dielectric layer encasing the respective memory cells and a second dielectric layer encasing the first dielectric layer and the respective memory cells.

14. The memory of claim 1 , wherein a material of the first dielectric layer is common with a material of the second dielectric layer, wherein the first dielectric layer and the second dielectric layer form at least two continuous layers of the common material.

15. The method of claim 5 , wherein a material of the first dielectric layer is common with a material of the second dielectric layers, wherein the first dielectric layer and the second dielectric layer form at least two continuous layers of the common material.

16. The method of claim 5 , wherein forming the interfacial insulator further comprises:

depositing the first dielectric layer; and

depositing the second dielectric layer after altering the surface of the first dielectric layer.

17. The method of claim 16 , wherein the first and second dielectric layers are formed from a same material, and wherein said altering a surface comprises halting deposition of the same material to form an interface between the first and second dielectric layers.

18. The method of claim 5 , wherein said depositing the first dielectric layer, said depositing the second dielectric layer, or both, comprise using atomic layer deposition.

19. The memory of claim 11 , wherein a material of the first dielectric layer is common with a material of the second dielectric layers, wherein the first dielectric layer and the second dielectric layer form at least two continuous layers of the common material.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →