Manufacturing testing for LDPC codes

1. A system for testing, comprising:

a processor; and

a non-transitory memory coupled with the processor, wherein the non-transitory memory is configured to provide the processor with instructions which when executed cause the processor to:

receive a low-density parity-check (LDPC) code;

for the received LDPC code, generate an error rate function that is a function of a number of iterations;

determine a number of test iterations and a passing error rate using the error rate function; and

test one or more storage media using the LDPC code, the number of test iterations, and the passing error rate.

2. The system recited in claim 1 , wherein the storage media includes one or more of the following: a hard disk drive or a Flash drive.

3. The system recited in claim 1 , wherein the LDPC code and an LDPC code used during an operational mode are the same code.

4. The system recited in claim 1 , wherein the instructions for generating include instructions for empirically obtaining the error rate function, including by:

encoding data using the LDPC code;

writing the encoded data to test development storage media;

reading back the encoded data from the test development storage media; and

decoding the read data.

5. The system recited in claim 4 , wherein decoding is performed once and for each iteration of the decoding a corresponding error rate is determined.

6. The system recited in claim 4 , wherein the instructions for generating further include instructions for:

obtaining a plurality of test development storage media; and

for each of the plurality of test development storage media, performing the steps of encoding, writing, reading, and decoding.

7. The system recited in claim 6 , wherein the instructions for generating further include instructions for:

for each of the plurality of test development storage media, generating an individual error rate function to obtain a plurality of individual error rate functions; and

averaging the plurality of individual error rate functions to obtain the error rate function.

8. The system recited in claim 6 , wherein the instructions for generating further include instructions for:

for each of the plurality of test development storage media, generating an individual error rate function to obtain a plurality of individual error rate functions; and

selecting one of the plurality of individual error rate functions to be the error rate function.

9. The system recited in claim 1 , wherein the instructions for determining include instructions for:

determining an amount of test time;

determining how many sectors can be written and read using the amount of test time;

determining a lower error rate can be measured reliably; and

selecting a number of iterations that corresponds to the lower error rate based on the error rate function.

10. The system recited in claim 9 , wherein the instructions for determining further include instructions for adding a margin to the lower error rate to obtain the passing error rate.

11. A computer program product for testing, the computer program product being embodied in a non-transitory computer readable storage medium and comprising computer instructions for:

receiving a low-density parity-check (LDPC) code;

for the received LDPC code, generating an error rate function that is a function of a number of iterations;

determining a number of test iterations and a passing error rate using the error rate function; and

testing one or more storage media using the LDPC code, the number of test iterations, and the passing error rate.

12. The computer program product recited in claim 11 , wherein the LDPC code and an LDPC code used during an operational mode are the same code.

13. The computer program product recited in claim 12 , wherein the computer instructions for determining include computer instructions for:

determining an amount of test time;

determining how many sectors can be written and read using the amount of test time;

determining a lower error rate can be measured reliably; and

selecting a number of iterations that corresponds to the lower error rate based on the error rate function.

14. The computer program product recited in claim 13 , wherein the computer instructions for determining further include computer instructions for adding a margin to the lower error rate to obtain the passing error rate.

15. The computer program product recited in claim 11 , wherein the computer instructions for generating include computer instructions for empirically obtaining the error rate function, including by:

encoding data using the LDPC code;

writing the encoded data to test development storage media;

reading back the encoded data from the test development storage media; and

decoding the read data.

16. The computer program product recited in claim 15 , wherein decoding is performed once and for each iteration of the decoding a corresponding error rate is determined.

17. A method for testing, comprising:

receiving a low-density parity-check (LDPC) code;

for the received LDPC code, using a processor to generate an error rate function that is a function of a number of iterations;

using the processor to determine a number of test iterations and a passing error rate using the error rate function; and

testing one or more storage media using the LDPC code, the number of test iterations, and the passing error rate.

18. The method recited in claim 17 , wherein using the processor to generate includes empirically obtaining the error rate function, including by:

encoding data using the LDPC code;

writing the encoded data to test development storage media;

reading back the encoded data from the test development storage media; and

decoding the read data.

19. The method recited in claim 18 , wherein using the processor to generate further includes:

obtaining a plurality of test development storage media; and

for each of the plurality of test development storage media, performing the steps of encoding, writing, reading, and decoding.

20. The system recited in claim 19 , wherein using the processor to generate further includes:

for each of the plurality of test development storage media, generating an individual error rate function to obtain a plurality of individual error rate functions; and

averaging the plurality of individual error rate functions to obtain the error rate function.

21. The system recited in claim 19 , wherein using the processor to generate further includes:

for each of the plurality of test development storage media, generating an individual error rate function to obtain a plurality of individual error rate functions; and

selecting one of the plurality of individual error rate functions to be the error rate function.