Digitally adjustable quantization circuit
View Patent ↗Apparatus and methods are provided for converting an analog input signal to a digital output value. A quantization circuit comprises an input node and a comparator array, wherein each comparator of the comparator array is coupled to the input node. A voltage divider arrangement is coupled to the comparator array and configured to establish a respective threshold voltage for each comparator of the comparator array. The comparator array generates a digital code based on the input signal and the respective threshold voltage for each comparator. A control node is coupled to the voltage divider arrangement, wherein the control node and the voltage divider arrangement are cooperatively configured to adjust the threshold voltage for at least one comparator of the comparator array in response to a control signal at the control node.
1. A quantization circuit comprising:
an input node for an input signal;
a comparator array coupled to the input node, wherein each comparator of the comparator array is coupled to the input node;
a voltage divider arrangement coupled to the comparator array, the voltage divider arrangement having a plurality of threshold voltage reference nodes, each threshold voltage reference node being configured to establish a respective threshold voltage for each comparator of the comparator array, wherein a voltage potential difference between adjacent threshold reference nodes is substantially equal throughout the voltage divider, and wherein the comparator array generates a digital code based on the input signal and the respective threshold voltage for each comparator; and
a control node coupled to the voltage divider arrangement, wherein the control node and the voltage divider arrangement are cooperatively configured to adjust the voltage potential difference between adjacent threshold voltage reference nodes by adjusting the threshold voltage for at least one comparator of the comparator array in response to a control signal at the control node.
2. The quantization circuit of claim 1 , wherein the voltage divider arrangement comprises:
a voltage divider coupled to the comparator array; and
a first variable resistance element coupled to the voltage divider, the first variable resistance element being coupled to the control node, wherein the control node and the voltage divider arrangement are cooperatively configured to adjust the threshold voltage for the at least one comparator of the comparator array by adjusting the effective resistance of the first variable resistance element in response to the control signal.
3. The quantization circuit of claim 2 , wherein the first variable resistance element comprises:
a first resistance element coupled between a first node and the voltage divider;
a switch coupled to the first node; and
a second resistance element coupled between the switch and the voltage divider, such that the second resistance element and the first resistance element are configured electrically in parallel when the switch is closed.
4. The quantization circuit of claim 3 , wherein the control node and the first variable resistance element are cooperatively configured to adjust the effective resistance of the first variable resistance element by activating the switch in response to the control signal.
5. The quantization circuit of claim 4 , wherein the control node and the first variable resistance element are cooperatively configured to decrease the effective resistance of the first variable resistance element by closing the switch in response to the control signal.
6. The quantization circuit of claim 4 , wherein the control node and the first variable resistance element are cooperatively configured to increase the effective resistance of the first variable resistance element by opening the switch in response to the control signal.
7. The quantization circuit of claim 2 , wherein the voltage divider arrangement further comprises:
a second variable resistance element coupled to the voltage divider, the second variable resistance element being coupled to the control node, wherein the voltage divider arrangement and the control node are cooperatively configured to adjust the effective resistance of the second variable resistance element in response to the control signal.
8. The quantization circuit of claim 7 , further comprising:
a first reference node, the first variable resistance element being coupled between the first reference node and the voltage divider; and
a second reference node, the second variable resistance element being coupled between the second reference node and the voltage divider.
9. The quantization circuit of claim 1 , further comprising an encoder coupled to the comparator array, wherein the encoder is configured to produce a digital value based on the digital code.
10. The quantization circuit of claim 9 , further comprising:
a digital adder having a first summing input, a second summing input, and a summation output, wherein:
the first summing input is coupled to the encoder and receives the digital value; and
the summation output is configured to produce a plurality of bits by adding the digital value and a feedback value at the second summing input; and
a digital delay element coupled to the summation output, the second summing input, and the control node, wherein the digital delay element is configured to delay a first portion of bits of the plurality of bits at the summation output to obtain the feedback value, wherein the feedback value is provided to the second summing input and the threshold voltage for the at least one comparator of the comparator array is adjusted based on the feedback value.
11. An analog-to-digital converter comprising:
an input node for receiving an input signal;
a control node for receiving a control signal;
a digital output; and
a quantizer coupled between the input node and the digital output, the quantizer being configured to generate a digital code with a first voltage resolution based at least in part on the input signal and a respective threshold voltage for a comparator, wherein the quantizer is coupled to the control node and configured to:
generate a digital value at the digital output based on the digital code; and
generate the digital code with a second voltage resolution by adjusting the respective threshold voltage for the comparator in response to the control signal.
12. The analog-to-digital converter of claim 11 , wherein the quantizer comprises a plurality of comparators configured to generate a thermometer code with the first voltage resolution based at least in part on the input signal and a respective threshold voltage for each comparator of the plurality of comparators, and wherein the quantizer is configured to:
generate the digital value based on the thermometer code; and
adjust the respective threshold voltage for at least one comparator of the plurality of comparators in response to the control signal, the plurality of comparators generating the thermometer code with the second voltage resolution in response to adjusting the respective threshold voltage for at least one comparator of the plurality of comparators.
13. The analog-to-digital converter of claim 12 , further comprising a forward signal arrangement coupled between the input node and the quantizer, the forward signal arrangement being configured to produce a first analog signal based at least in part on the input signal, wherein the plurality of comparators generates the thermometer code based on the first analog signal.
14. The analog-to-digital converter of claim 13 , further comprising a digital-to-analog converter coupled between the digital output and the forward signal arrangement, the digital-to-analog converter being configured to convert the digital value to an analog feedback signal, wherein the forward signal arrangement produces the first analog signal based on the input signal and the analog feedback signal.
15. The analog-to-digital converter of claim 12 , wherein the quantizer is configured to:
generate the thermometer code using the first voltage resolution for a first operating mode; and
generate the thermometer code using the second voltage resolution for a second operating mode.
16. The analog-to-digital converter of claim 15 , further comprising a control module coupled to the control node, the control module being configured to:
identify the second operating mode; and
adjust the threshold voltage for at least one comparator of the plurality of comparators in response to identifying the second operating mode.
17. The analog-to-digital converter of claim 16 , wherein the quantizer further comprises:
a voltage divider coupled to the plurality of comparators and configured to establish the respective threshold voltage for each comparator of the plurality of comparators; and
a first variable resistance element coupled to the voltage divider, the first variable resistance element being coupled to the control module, wherein the control module is configured to adjust the effective resistance of the first variable resistance element in response to identifying the second operating mode.
18. A method for converting an analog input signal at an input node of a quantization circuit to a digital output value, the method comprising:
generating a digital code using a comparator array configured for a first operating mode, wherein the digital code is based on the analog input signal and a respective threshold voltage for each comparator of the comparator array, the threshold voltage for the comparators of the comparator array corresponding to a first voltage resolution in the first operating mode;
identifying a second operating mode;
adjusting, in response to identifying the second operating mode, the threshold voltage for at least one comparator of the comparator array;
generating the digital code having a second voltage resolution in response to adjusting the threshold voltage for at least one comparator array; and
generating the digital output value based on the digital code.
19. The method of claim 18 , wherein the generating the digital code comprises:
generating a thermometer code based on the analog input signal using the first voltage resolution in the first operating mode; and
generating the thermometer code based on the analog input signal using the second voltage resolution in response to adjusting the threshold voltage for at least one comparator of the comparator array.
20. The method of claim 18 , the quantization circuit comprising a voltage divider arrangement coupled to the comparator array, the voltage divider arrangement being configured to establish the respective threshold voltage for each comparator of the comparator array, the voltage divider arrangement including a variable resistance element, wherein adjusting the respective threshold voltage for the at least one comparator of the comparator array comprises adjusting the effective resistance of the variable resistance element in response to identifying the second operating mode.
21. A quantization circuit comprising:
an input node for an input signal;
a comparator array coupled to the input node, wherein each comparator of the comparator array is coupled to the input node;
a voltage divider arrangement coupled to the comparator array and configured to establish a respective threshold voltage for each comparator of the comparator array, wherein the comparator array generates a digital code based on the input signal and the respective threshold voltage for each comparator;
a control node coupled to the voltage divider arrangement, wherein the control node and the voltage divider arrangement are cooperatively configured to adjust the threshold voltage for at least one comparator of the comparator array in response to a control signal at the control node;
an encoder coupled to the comparator array, wherein the encoder is configured to produce a digital value based on the digital code;
a digital adder having a first summing input, a second summing input, and a summation output, wherein:
the first summing input is coupled to the encoder and receives the digital value; and
the summation output is configured to produce a plurality of bits by adding the digital value and a feedback value at the second summing input; and
a digital delay element coupled to the summation output, the second summing input, and the control node, wherein the digital delay element is configured to delay a first portion of bits of the plurality of bits at the summation output to obtain the feedback value, wherein the feedback value is provided to the second summing input and the threshold voltage for the at least one comparator of the comparator array is adjusted based on the feedback value.