Semiconductor device with MISFET
View Patent ↗A semiconductor device includes a substrate, a semiconductor region provided in the substrate, a group of transistors including a plurality of MIS transistors and provided in the semiconductor region, the MIS transistors including a plurality of gate electrodes which extend in a first direction and are provided on the semiconductor region via gate insulation films, an insulation film provided on the group of transistors, and a first contact layer and a second contact layer extending in the first direction and provided on the semiconductor region at opposite sides of the group of transistors.
1. A semiconductor device comprising:
a substrate;
a semiconductor layer provided on the substrate, extending in a first direction, and including an upper surface and opposite side surfaces;
a group of transistors including a plurality of MIS transistors and provided in the semiconductor layer;
an insulation film provided on the group of transistors; and
a first contact layer and a second contact layer provided on the upper surface and the opposite side surfaces of the semiconductor layer at opposite sides of the group of transistors, and extending in a second direction perpendicular to the first direction,
wherein the first and second contact layers have a length larger than a width of the semiconductor layer.
2. The semiconductor device according to claim 1 , wherein the MIS transistors include a plurality of gate electrodes provided on the semiconductor layer via gate insulation films and extending in the second direction.
3. The semiconductor device according to claim 1 , wherein:
each of the MIS transistors includes two source/drain regions provided in the semiconductor layer;
the first contact layer is provided on a source/drain region of one of the MIS transistors which is located at one end of the group of transistors; and
the second contact layer is provided on a source/drain region of one of the MIS transistors which is located at another end of the group of transistors.
4. The semiconductor device according to claim 1 , wherein:
the semiconductor layer is of a p-type;
the MIS transistors are of an n-type; and
the insulation film causes channel regions of the MIS transistors to produce tensile stress.
5. The semiconductor device according to claim 1 , wherein:
the semiconductor layer is of an n-type;
the MIS transistors are of a p-type; and
the insulation film causes channel regions of the MIS transistors to produce compressive stress.
6. The semiconductor device according to claim 1 , wherein the first and second contact layers have a rectangular planar configuration.