Flash memory device
View Patent ↗Embodiments relate to a flash memory device and a method of manufacturing a flash memory device, which may increase a coupling coefficient between a control gate and a floating gate by increasing a surface area of floating gate. In embodiments, a flash memory device may be formed by forming a photoresist pattern for forming a floating gate on a semiconductor substrate including an oxide film, a floating gate poly film, and a BARC (Bottom AntiReflect Coating), performing a first etching process using the photoresist pattern as a mask, to etch the floating gate poly film to a predetermined depth, depositing and forming a polymer to cover the photoresist pattern, forming spacers of the polymer at both sidewalls of the photoresist pattern, forming a second etching process using the spacers as a mask, to expose the oxide film, and removing the BARC, the photoresist pattern and the spacers by ashing and stripping.
1. A floating gate, comprising:
a first polysilicon tier formed over an oxide layer, having a first width;
a second polysilicon tier formed over the first polysilicon tier, having a second width narrower than the first width; and
a plurality of polysilicon tiers formed over the second polysilicon tier, each of the plurality of polysilicon tiers having a narrower width than a preceding polysilicon tier.
2. The floating gate of claim 1 , wherein each of the tiers is formed from a single polysilicon layer that is etched to form the tier structure.
3. The floating gate of claim 2 , wherein a height of each polysilicon tier is approximately 300 to 500Å.
4. The floating gate of claim 2 , wherein an upper surface of the second polysilicon tier of the floating gate comprises a plurality of grooves formed in the upper surface.