Semiconductor integrated circuit having improved power supply wiring
View Patent ↗In a semiconductor integrated circuit including a plurality of cells, a supplementary power-supply wire is disposed between a lattice-shaped upper power-supply wire and a lower cell power-supply wire for cases in which power is supplied from the upper power-supply wire to the lower cell power-supply wire. The supplementary power-supply wire and the lower cell power-supply wire are connected by two vias. The supplementary power-supply wire and the upper power-supply wire are connected by a single via. Current from the supplementary power-supply wire is divided by the two vias and then supplied to the lower cell power-supply wire. Therefore, when power is supplied from the upper power-supply wire to the lower cell power-supply wire, current concentration at the connection points of the lower cell power-supply wire to the vias is decreased, thereby reducing wire breaks caused by EM (electro migration).
1. A semiconductor integrated circuit, comprising:
a plurality of standard cells aligned in a horizontal direction when viewed in plan;
a standard cell power-supply wire, extending in the horizontal direction when viewed in plan, formed in a region in which the standard cells are disposed; and
a supplementary power-supply wire, extending in the horizontal direction when viewed in plan, disposed on an upper layer in which the standard cell power-supply wire is disposed,
wherein the standard cell power-supply wire and the supplementary power-supply wire are connected with each other by at least two vias, and
power is supplied from the supplementary power-supply wire to the standard cell power-supply wire through the at least two vias, and
when viewed in plan, a wire length of the standard cell power-supply wire in the horizontal direction is longer than a wire length of the supplementary power-supply wire in the horizontal direction.
2. The semiconductor integrated circuit of claim 1 , wherein
an upper power-supply wire is disposed on an upper layer in which the standard cell power-supply wire is disposed,
the upper power-supply wire and the supplementary power-supply wire are connected with each other by at least one via, and
power is supplied from the upper power-supply wire to the supplementary power-supply wire through the at least one via.
3. The semiconductor integrated circuit of claim 2 , wherein the upper power-supply wire extends in the vertical direction.
4. The semiconductor integrated circuit of claim 2 , wherein the two vias that connect the standard cell power-supply wire and the supplementary power-supply wire are disposed in opposite directions with respect to the at least one via that connects the supplementary power-supply wire and the upper power-supply wire, the two vias being located at a given distance from the at least one via.
5. The semiconductor integrated circuit of claim 2 , wherein the at least one via that connects the supplementary power-supply wire and the upper power-supply wire is disposed in the middle position between the two vias that connect the standard cell power-supply wire and the supplementary power-supply wire when viewed in plan.
6. The semiconductor integrated circuit of claim 1 , wherein the supplementary power-supply wire has a larger wire width than the standard cell power-supply wire.
7. The semiconductor integrated circuit of claim 1 , wherein a plurality of cells are disposed between the two vias that connect the standard cell power-supply wire and the supplementary power-supply wire.
8. The semiconductor integrated circuit of claim 1 , wherein a plural number of standard intra-cell power-supply wires, which are disposed within each of the standard cells and connected to the standard cell power-supply wire, are located between the two vias that connect the standard cell power-supply wire and the supplementary power-supply wire.