Non-volatile Memory Array Having Circuitry To Complete Programming Operation In The Event Of Power Interrupt
An electrically programmable non-volatile memory device comprises a memory circuit which includes an array of non-volatile memory cells. Each memory cell is capable of being programmed. A programming circuit can generate a programming signal to program one or more of the memory cells. A voltage detector circuit is connected to a voltage source which outputs a certain voltage. The voltage detector circuit detects when the certain voltage has decreased to a certain level, and in response thereto, the voltage detector provides an output signal to the memory controller to complete the on-going programming command sequence and to power down itself. An auxiliary voltage source maintains voltage to the memory circuit for a period of time sufficient for the programming circuit to complete the programming of the one or more of the memory cells, when the certain voltage is at or below the certain level.
1 . An electrically programmable non-volatile memory device comprising:
a memory circuit including an array of non-volatile memory cells, each cell capable of being programmed, and a programming circuit for programming one or more of said memory cells;
a voltage detector circuit connected to a voltage source having a certain voltage, said voltage detector circuit for detecting when said certain voltage has decreased to a certain level, and in response thereto, said voltage detector providing an output signal to said memory circuit;
said memory circuit responsive to said output signal to complete any programming operation and to power down said memory circuit thereafter; and
an auxiliary voltage source for maintaining voltage to said memory circuit for a period of time sufficient for said programming circuit to complete the programming of said one or more of said memory cells, when said certain voltage is at or below said certain level.
2 . The memory device of claim 1 wherein each of said memory cells is a non-volatile memory transistor having a floating gate for storing charges thereon.
3 . The memory device of claim 2 wherein said array of non-volatile memory cells is an array of NAND memory cells.
4 . The memory device of claim 2 wherein said array of non-volatile memory cells is an array of NOR memory cells.
5 . The memory device of claim 3 wherein each of said memory cells is a MLC memory cell storing a plurality of bits.
6 . The memory device of claim 5 wherein said array of NAND memory cells is divided into a plurality of pages.
7 . The memory device of claim 6 wherein the plurality of bits in each memory cell are associated with a plurality of different pages.
8 . The memory device of claim 7 wherein each MLC memory cell stores two or more bits.
9 . The memory device of claim 8 wherein each of the two or more bits in a MLC memory cell is associated with a different page.
10 . The memory device of claim 1 wherein memory circuit comprises a memory array and a memory controller.
11 . The memory device of claim 10 , wherein said memory controller is responsive to said output signal to complete any programming operation of said memory array and to power down said memory array thereafter.
12 . The memory device of claim 11 wherein said memory controller is also responsive to said output signal to power down said memory controller after the completion of any programming operation of said memory array.