Semiconductor device and manufacturing methods with using non-planar type of transistors
View Patent ↗Static random access memory cells and methods of making static random access memory cells are provided. The static random access memory cells contain two non-planar pass-gate transistors, two non-planar pull-up transistors, two non-planar pull-down transistors. A portion of a fin of the non-planar pull-up transistor is electrically connected to a portion of a fin of the non-planar pull-down transistor by an assist-bar. The methods involve forming an assist-fin between fins of a non-planar pull-up transistor and a non-planar pull-down transistor and between gate electrodes, and widening a width of the assist-fin to form the assist-bar so that a portion of the fin of non-planar pull-up transistor is electrically connected to a portion of the fin of non-planar pull-down transistor via the assist-bar.
1. A static random access memory cell, comprising:
two non-planar pass-gate transistors on a semiconductor substrate, each of the two non-planar pass-gate transistors comprising one or more non-planar pass-gate fins;
two non-planar pull-up transistors on the semiconductor substrate, each of the two non-planar pull-up transistors comprising one or more non-planar pull-up transistor fins;
two non-planar pull-down transistors on the semiconductor substrate, each of the two non-planar pull-down transistors comprising one or more non-planar pull-down transistor fins; and
two assist-bars on the semiconductor substrate, each of the two assist bars comprising one or more assist-bar fins extending parallel to the one or more non-planar pass gate fins of at least one of the two non-planar pass-gate transistors, the one or more non-planar pull-up transistor fins of at least one of the two non-planar pull-up transistors and the one or more non-planar pull down transistor fins of at least one of the two non-planar pull-down transistors and the two assist-bars electrically connecting a portion of the one or more fins of at least one of the two non-planar pull-up transistors and a portion of the one or more fins of at least one of the two non-planar pull-down transistors, wherein the two assist-bars are provided in a same layer level as the one or more non-planar pull-up transistor fins and the one or more non-planar pull-down transistor fins.
2. The static random access memory cell of claim 1 , wherein the two assist-bars are formed substantially vertically to the surface of the semiconductor substrate and the one or more pull-down transistor fins of at least one of the two or more pull-down transistors and the one or more pull-up transistor fins of at least one of the two or more pull-up transistors.
3. The static random access memory cell of claim 1 , wherein the two assist-bars comprise a semiconductor material and metal-semiconductor compound.
4. The static random access memory cell of claim 1 , wherein the static random access memory cell does not comprise at least one of a contact hole and a conductive line that electrically connect the at least one non-planar pull-up transistor fin and the at least one non-planar pull-down transistor.
5. The static random access memory cell of claim 1 , wherein the two non-planar pull-down transistors are N-typed FinMOSFETs and the two non-planar pull-up transistors are P-typed FinMOSFETs.
6. The static random access memory cell of claim 5 , wherein the one or more non-planar pull-down transistor fins and the two non-planar pass-gate transistors have two types of contact holes: a first contact hole type comprising at least one contact hole that electrically connects a bitline to a n-diffusion layer and a second contact hole type comprising at least one contact hole that electrically connects the n-diffusion layer to a ground line.
7. The static random access memory cell of claim 1 , wherein the two assist-bars facilitate electrically connecting diffusion layers of the two non-planar pass-gate transistors, the two non-planar pull-down transistors, and the two non-planar pull-up transistors.
8. The static random access memory cell of claim 5 , wherein the static random access memory cell comprises ten contact holes, one contact hole on respective two gate electrodes, two contact holes on the respective two N-typed FinMOSFETs, and two contact holes on the respective two P-typed FinMOSFETs.
9. A random logic circuit; comprising:
a first non-planar transistor on a semiconductor substrate comprising a first fin;
a second non-planar transistor on the semiconductor substrate comprising a second fin; and
one or more assist-bars on the semiconductor substrate, the one or more assist-bars electrically connecting a portion of the first fin and a portion of the second fin and the one or more assist-bars comprise one or more assist-bar fins that are parallel to the first fin and the second fin, wherein the one or more assist bars, the first fin and the second fin are provided in a same layer level.