IP Library Granted Patent US 7,817,979
Granted Patent B2
US 7,817,979 · App. 12/399,688 · Granted Oct 19, 2010

Systems and methods for DC offset correction in a direct conversion RF receiver

Assignee: General Dynamics C4 Systems
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,817,979
App. No.
12/399,688
Granted
Oct 19, 2010
Kind
B2
Abstract

Systems and methods for DC offset correction in analog and digital direct conversion RF receivers. A time derivate and subsequent integration of in-phase and quadrature phase signal path components is performed to effectively remove DC offset from the resultant down converted baseband signal.

Claims (37)

1. A direct conversion RF receiver comprising:

an RF antenna adapted to receive an RF signal;

a preselect filter adapted to filter the incoming RF signal;

a low noise amplifier adapted to amplify the received RF signal;

a local oscillator producing a local oscillation signal having a frequency tuned to that of the received RF signal;

a first RF mixer along an in-phase channel path adapted to multiply a received radio frequency signal with the local oscillation signal;

a second RF mixer along a quadrature-phase channel path adapted to multiply the received radio frequency signal with a 90° phase-shifted version of the local oscillation signal;

a first low pass filter filtering an output of the first mixer thereby outputting a downconverted in-phase signal I, centered at baseband;

a second low pass filter filtering an output of the second mixer thereby outputting a downconverted quadrature phase signal Q centered at baseband; and

a residual DC correction circuit adapted to perform a time derivative and subsequent integration of the I and Q signals, wherein the time derivative and subsequent integration are performed after analog-to-digital conversion and comprise solving one or more algebraic expressions.

2. The direct conversion receiver according to claim 1 , wherein the DC correction circuit comprises programmable logic adapted to perform a DC correction algorithm.

3. The direct conversion receiver according to claim 1 , wherein the DC correction circuit comprises a set of mathematical operations performed on a processor.

4. A method of reducing direct current offset in a direct conversion receiver comprising:

receiving an RF signal at the receiver;

subjecting the RF signal to a preselect filtering process;

splitting the resultant signal into parallel in-phase (I), and quadrature-phase (Q) signal paths;

demodulating the respective signals on the I and Q signal paths with mixers located on each signal path and connected to a local oscillator;

filtering the respective results of the demodulation with a low pass filter to yield downconverted I and Q components of the received RF signal;

taking a time derivative of each of the respective downconverted signals; and

integrating the results of each time derivative, wherein the time derivative and subsequent integration are performed after analog-to-digital conversion and comprise solving one or more algebraic expressions.

5. A method of canceling DC offset in an RF receiver having a direct converter for direct down conversion of a received RF signal to a baseband signal, the method comprising:

taking a time derivative of signals in respective in-phase and quadrature-phase signal paths of the direct converter; and

integrating the results of the derivative to obtain the received signal without any constant offset value, wherein the time derivative and subsequent integration are performed after analog-to-digital conversion and comprise solving one or more algebraic expressions.

6. A DC offset reduction block for a direct conversion circuit of an RF receiver comprising:

circuitry adapted to take a time derivative of respective signals propagating through in-phase and quadrature phase signal paths of the direct conversion circuit; and

circuitry adapted to integrate the results of the differentiation, thereby yielding respective I and Q components devoid of constant offset values, wherein the time derivative and subsequent integration are performed after analog-to-digital conversion and comprise solving one or more algebraic expressions.

7. A direct conversion IF converter comprising:

an intermediate frequency, IF, filter adapted to filter the IF signal;

an IF amplifier adapted to amplify the IF signal;

a local oscillator producing a local oscillation signal having a frequency tuned to that of the IF signal;

a first IF mixer along an in-phase channel path adapted to multiply a received radio frequency signal with the local oscillation signal;

a second IF mixer along a quadrature-phase channel path adapted to multiply the received radio frequency signal with a 90° phase-shifted version of the local oscillation signal;

a first low pass filter filtering an output of the first mixer thereby outputting a downconverted in-phase signal I, centered at baseband;

a second low pass filter filtering an output of the second mixer thereby outputting a downconverted quadrature phase signal Q centered at baseband; and

a residual DC correction circuit adapted to perform a time derivative and subsequent integration of the I and Q signals, wherein the time derivative and subsequent integration are performed after analog-to-digital conversion and comprise solving one or more algebraic expressions.

8. The direct conversion IF converter according to claim 7 , wherein the DC correction circuit comprises programmable logic adapted to perform a DC correction algorithm.

9. The direct conversion IF converter according to claim 7 , wherein the DC correction circuit comprises a set of mathematical operations performed on a processor.

Assignments (1)
CONFIRMATORY LICENSE Recorded Apr 12, 2011
From: GENERAL DYNAMICS C4 SYSTEMS, INC
To: UNITED STATES OF AMERICA AS REPRESENTED BY THE SECRETARY
Reel/Frame 026112/0747 →
Continuity (2)
Continuation 1149122800 · Jul 24, 2006
Related Publication 20100061485A1 · Mar 11, 2010