Architecture for vector memory array transposition using a block transposition accelerator

1. A system for vector memory array transposition, the system comprising:

a vector memory to store a vector memory array;

a block transposition accelerator coupled to the vector memory, the block transposition accelerator configured to firstly read vectors of a block of data by shifting the vectors into the vector memory array along a first dimension such that each vector is shifted serially into the vector memory in the same direction as the first dimension and to secondly write a transposition of the vectors by shifting the transposition of the vectors out of the vector memory along a second dimension such that each transposed vector is shifted serially out of the vector memory in the same direction as the second dimension, wherein the second dimension is perpendicular to the first dimension in the vector memory array; and

an address controller coupled to the block transposition accelerator, the address controller configured to determine a vector access order,

wherein the block transposition accelerator is configured to access the vector of the block of data within the vector memory array according to the vector access order.

2. A system in accordance with claim 1 further comprising a second block transposition accelerator coupled to the vector memory, the second block transposition accelerator configured to firstly read a second plurality of vectors of a second block of data by shifting the second plurality of vectors into the vector memory array along the first dimension and to secondly write a second transposition of the second plurality of vectors by shifting the second transposition of the vectors out of the vector memory along the second dimension.

3. A system in accordance with claim 2 wherein the first and second block transposition accelerators are further configured to work successively in complementary phases on neighboring blocks, in which the second block transposition accelerator is configured to execute read operations for the second plurality of vectors of the second block of data within the vector memory during write operations of the first block transposition accelerator.

4. The system in accordance with claim 1 , wherein the address controller is further configured to determine a vector access order without changing the address of data elements.

5. A method for transposing a vector memory array, the method comprising:

reading a plurality of vectors of a block of data within the vector memory array stored in a vector memory;

reading, by a first block transposition accelerator in input mode, the plurality of vectors of the block of data into the first block transposition accelerator by separately shifting each one of the plurality of vectors of the block of data serially into separate rows of a plurality of matrix registers in a first direction; and

outputting immediately after reading, by the first block transposition accelerator in output mode, a plurality of transposed vectors of the block of data serially from columns of the plurality of matrix registers that are perpendicular to the rows, wherein the plurality of transposed vectors are based on the plurality of vectors of block data.

6. A method in accordance with claim 5 further comprising writing the plurality of transposed vectors to the vector memory.

7. A method in accordance with claim 6 further comprising reading, by a second block transposition accelerator, a second plurality of vectors of a second block of data within the vector memory array stored in the vector memory to a second plurality of registers during the writing of the plurality of transposed vectors to the vector memory.