IP Library Granted Patent US 7,825,723
Granted Patent B1
US 7,825,723 · App. 12/400,706 · Granted Nov 2, 2010

Method and apparatus using an I/O device to eliminate a level shifter in low-voltage CMOS integrated circuits

Assignee: Atheros Communications, Inc.
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Quick Facts
Patent No.
US 7,825,723
App. No.
12/400,706
Granted
Nov 2, 2010
Kind
B1
Abstract

This discloses an integrated circuit and at least one CMOS analog circuit including a first circuit component generating an output signal received by a second circuit component to generate a feedback signal received by the first component to regulate the output signal, where the transistors of the first circuit component consist of first MOS transistor instances compliant with a first core voltage and the feedback signal requires the transistors of the second circuit component to consist of at least one second MOS transistor instance compliant with a second core voltage above the first core voltage. The CMOS analog circuit may implement an amplifier, a transconductance amplifier and/or a telescopic amplifier. The first core voltage may at most 1.2 volts and the second core voltage may be at least three volts. The first MOS transistors may be thin oxide transistors and the second MOS transistors may be thicker oxide transistors.

Claims (23)

1. An integrated circuit, comprising:

at least one CMOS analog circuit including

an amplifier generating an output based upon an input, comprising:

a first circuit component forming a transconductance stage configured to receive said input, to receive a feedback signal as a tail current Itail, and to generate said output,

with said first circuit component consisting of at least two first transistor instances compliant with a first core voltage of at most one and two tenth volts; and

a second circuit component configured as a current source to receive said output and generate said feedback signal as said tail current Itail requiring said second circuit component to consist of at least one second transistor instance compliant with a second core voltage of at least three volts.

2. The integrated circuit of claim 1 , wherein each of said first MOS transistor instances has a first oxide thickness; and

each of said second MOS transistor instances has a second oxide thickness greater than said first oxide thickness.

3. The integrated circuit of claim 1 , wherein each of said first MOS transistor instances is a member of the group consisting of an NMOS device and a PMOS device.

4. The integrated circuit of claim 1 , wherein each of said second MOS transistor instances is a member of the group consisting of an NMOS device and a PMOS device.

5. The integrated circuit of claim 1 , wherein said transconductance amplifier further implements a telescopic amplifier.

6. An analog CMOS circuit, comprising:

an amplifier generating an output based upon an input, comprising:

a first circuit component forming a transconductance stage configured to receive said input, to receive a feedback signal as a tail current Itail, and to generate said output,

with said first circuit component consisting of at least two first MOS transistor instances compliant with a first core voltage;

a second circuit component configured as a current source to receive said output and generate said feedback signal as said tail current Itail requiring said second circuit component to consist of at least one second MOS transistor instance compliant with a second core voltage above said first core voltage;

wherein each of said first MOS transistor instances has a first oxide thickness; and

wherein each of said second MOS transistor instances has a second oxide thickness greater than said first oxide thickness.

7. The analog CMOS circuit of claim 6 , wherein said second core voltage is at least twice said second core voltage.

8. The analog CMOS circuit of claim 7 , wherein said second core voltage is at least two and nine tenths volts.

9. The analog CMOS circuit of claim 6 , wherein each of said first MOS transistor instances is a member of the group consisting of an NMOS device and a PMOS device.

10. The analog CMOS circuit of claim 6 , wherein each of said second MOS transistor instances is a member of the group consisting of an NMOS device and a PMOS device.

11. The analog CMOS circuit of claim 6 , wherein said transconductance amplifier further implements a telescopic amplifier.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 30, 2012
From: QUALCOMM ATHEROS, INC.
To: QUALCOMM INCORPORATED
Reel/Frame 029381/0932 →
MERGER Recorded Nov 29, 2012
From: ATHEROS COMMUNICATIONS, INC.
To: QUALCOMM ATHEROS, INC.
Reel/Frame 029375/0689 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED ON REEL 022367 FRAME 0817. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNEE NAME TO SHOW AS ATHEROS COMMUNICATIONS, INC. NOT ATHEROS COMMUNICATION, INC. Recorded Aug 29, 2011
From: MAKAREM, RABIH F.
To: ATHEROS COMMUNICATIONS, INC.
Reel/Frame 026823/0403 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 9, 2009
From: MAKAREM, RABIH F.
To: ATHEROS COMMUNICATION, INC.
Reel/Frame 022367/0817 →