Digital programmable phase generator
A programmable phase shifter is constructed of Rapid Single Flux Quantum (RSFQ) logic elements. The logic elements may include an RSFQ inverter and an RSFQ T flip-flop. A digital word comprising N bits is used to control the amount of phase shift and the phase shifter selectively imparts a respective phase shift for any of 2 N states that can be represented by the digital word. The RSFQ logic elements utilize Josephson junctions which operate in the superconducting temperature domain.
1. A digital programmable time delay circuit, comprising a circuit having a plurality of Josephson junctions, configured to provide a selectively controlled time delay which is an integer multiple N of a clock period T of a reference clock, wherein the selectively controlled time delay can assume any of at least 3 different delays based on an input digital control signal.
2. The digital programmable time delay circuit according to claim 1 , in which N represents any selectable m-bit binary integer from 0 to 2 m −1, wherein m≧2.
3. The digital programmable time delay circuit according to claim 1 , in which the circuit is fabricated using a multilayer integrated circuit process.
4. The digital programmable time delay circuit according to claim 1 , wherein at least a portion of the Josephson junctions are configured as Single Flux Quantum logic elements.
5. The digital programmable time delay circuit according to claim 4 , wherein at least a portion of the Single Flux Quantum logic elements are configured as T Flip-Flops.
6. The digital programmable time delay circuit according to claim 5 , wherein at least two T Flip-Flops are connected through a Single Flux Quantum inverter.
7. The digital programmable time delay circuit according to claim 6 , wherein a time delay is selectively controlled by digitally controlling a plurality of Single Flux Quantum inverters connecting a plurality of T Flip-Flops in series, each Single Flux Quantum inverter receiving a respective independent digital control signal.
8. The digital programmable time delay circuit according to claim 1 , wherein the input digital control signal comprises a Single Flux Quantum pulse.
9. The digital programmable time delay circuit according to claim 1 , wherein an output is provided representing a decimated representation of the reference clock delayed by the integer multiple N of the clock period.
10. A digital programmable time delay method, comprising:
providing a circuit having a plurality of Josephson junctions, configured to provide a selectively controlled time delay which is an integer multiple N of a clock period T of a reference clock, wherein the selectively controlled time delay can assume any of at least 3 different delays based on an input digital control signal;
receiving the input digital control signal representing a value 2 m , wherein m≧2;
receiving the reference clock; and
producing an output which has a delay defined as the integer multiple of the input digital control signal times the period T of the clock.
11. The method according to claim 10 , in which N represents any selectable m-bit binary integer from 0 to 2 m −1, wherein m≧3.
12. The method according to claim 10 , in which the circuit is fabricated using a multilayer integrated circuit process.
13. The method according to claim 10 , wherein at least a portion of the Josephson junctions of the circuit are configured as Single Flux Quantum logic elements.
14. The method according to claim 13 , wherein at least a portion of the Single Flux Quantum logic elements are configured as T Flip-Flops.
15. The method according to claim 14 , wherein at least two T Flip-Flops are connected through a Single Flux Quantum inverter.
16. The method according to claim 15 , wherein a time delay is selectively controlled by digitally controlling a plurality of Single Flux Quantum inverters connecting a plurality of T Flip-Flops in series, each Single Flux Quantum inverter receiving a respective independent digital control signal.
17. The method according to claim 10 , wherein the input digital control signal comprises a Single Flux Quantum pulse.
18. A digital programmable time delay circuit, comprising a Single Flux Quantum circuit, comprising a set of Flip-Flops connected with digitally controlled inverters, and receiving a multibit digital input which controls the digitally controlled inverters, to produce a representation of an input signal which is delayed in time by an integer multiple defined by the received multibit signal of a clock period of a reference clock.
19. The digital programmable time delay circuit according to claim 18 , wherein the Single Flux Quantum circuit comprises a plurality of Josephson junctions fabricated using a multilayer integrated circuit process, configured as a series of T Flip-Flops connected by digitally controllable inverters.
20. The digital programmable time delay circuit according to claim 19 , wherein the Single Flux Quantum circuit comprises at least four T Flip-Flops connected by four digitally controllable inverters.
21. The digital programmable time delay circuit according to claim 18 , wherein the Single Flux Quantum circuit comprises at least four T Flip-Flops connected by four digitally controllable inverters.