Three dimensional structure memory
A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.
1 . An apparatus comprising:
a data source formed in a first layer of material;
a data sink formed in a second layer of material, there being a volume within which the first and second layers of material overlie one another; and
within said volume, interconnect circuitry, whereby a plurality of data bytes are transferred between the data source and the data sink.
2 . The apparatus of claim 1 , wherein the data source is a memory circuit and the data sink is a logic circuit.
3 . The apparatus of claim 2 , wherein the logic circuit comprises at least one microprocessor.
4 . The apparatus of claim 1 , wherein the data source is a first logic circuit and the data sink is a second logic circuit.
5 . The apparatus of claim 4 , wherein at least one of the first logic circuit and the second logic circuit comprises at least one microprocessor.
6 . The apparatus of claim 4 , wherein both the first logic circuit and the second logic circuit comprise at least one microprocessor.
7 . The apparatus of claim 1 , wherein the data source is formed in a plurality of layers of semiconductor material.
8 . The apparatus of claim 1 , further comprising a plurality of logic layers.
9 . The apparatus of claim 8 , wherein at least one of the plurality of layers comprises at least one microprocessor.
10 . The apparatus of claim 8 , wherein at least one of the plurality of logic layers comprise at least one microprocessor.
11 . The apparatus of claim 1 , further comprising a plurality of memory layers and logic layers.
12 . The apparatus of claim 11 , wherein at least one of the plurality of logic layers comprises at least one microprocessor.
13 . The apparatus of claim 11 , wherein at least one of the plurality of logic layers comprise at least one microprocessor.
14 . The apparatus of claim 7 , wherein the plurality of layers of semiconductor material for the data source are formed from one of single crystal semiconductor material and polycrystalline semiconductor material.
15 . An apparatus comprising:
a data source formed in a first circuit layer;
a data sink formed in a second circuit layer, there being a volume within which the first and second circuit layers overlie one another; and
within said volume, there being interconnect circuitry whereby a plurality of data bytes are transferred between the data source and data sink.
16 . The apparatus of claim 15 , wherein the data source is a memory circuit and the data sink is a logic circuit.
17 . The apparatus of claim 16 , wherein the logic circuit comprises at least one microprocessor circuit.
18 . The apparatus of claim 15 , wherein the data source is a first logic circuit and the data sink is a second logic circuit.
19 . The apparatus of claim 15 , wherein the data source and the data sink are formed from one of single crystal semiconductor material and polycrystalline semiconductor material.
20 . The apparatus of claim 1 , wherein the one layer and the other layer are formed with one of single crystal semiconductor material and polycrystalline semiconductor material.
21 . The apparatus of claim 1 , wherein the one layer and the other layer are first and second integrated circuit layers, one of the first and second integrated circuits being formed using a different process technology than another of the first and second integrated circuits, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.
22 . The apparatus of claim 1 , wherein at least one of the one and the other layers comprises a microprocessor.
23 . The apparatus of claim 1 , further comprising at least one memory layer and at least one logic layer, wherein the at least one logic layer performs testing of the at least one memory layer.
24 . The apparatus of claim 1 , further comprising at least one memory layer having multiple memory locations including at least one memory location used for sparing wherein data from the at least one memory location on the at least one memory layer is used instead of data from a defective memory location on the at least one memory layer.
25 . The apparatus of claim 1 , further comprising at least one memory layer and at least one logic layer, wherein the at least one logic layer performs programmable gate line address assignment with respect to the at least one memory layer.
26 . The apparatus of claim 1 , wherein a plurality of interior vertical interconnections traverse at least one of the integrated circuits.
27 . The apparatus of claim 1 , wherein continuous vertical interconnections connect circuitry of the data source and the data sink.
28 . The apparatus of claim 1 , wherein information processing is performed on data routed between circuitry on the data source and the data sink.
29 . The apparatus of claim 1 , wherein at least one of the data source and the data has reconfiguration circuitry.
30 . The apparatus of claim 1 , further comprising at least one logic layer having logic for performing at least one of the following functions: virtual memory management, ECC, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing.
31 . The apparatus of claim 1 , further comprising:
a memory array having a plurality of memory cells, a plurality of data lines, and a plurality of gate lines, each memory storage cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to a gate control signal on one of said gate lines;
circuitry for generating a gate control signal in response to an address, including means for mapping addresses to gate lines; and
a controller for determining that one of said memory cells is defective and for altering said mapping to eliminate references to said one of said memory cells.
32 . The apparatus of claim 1 , further comprising:
one or more controller layers;
one or more memory layers;
a plurality of data lines and a plurality of gate lines on each memory layer;
an array of memory cells on each memory layer, each memory cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to the selection of one of said gate lines;
a gate line selection circuit for enabling a gate line for a memory operation, said gate line selection circuit comprising programmable gates to receive address assignments for one or more of said gate lines, said address assignments for determining which of said gate lines is selected for each programmed address assignment; and
controller logic for determining that one of said array memory cells is defective and for altering, in at least one instance, said address assignments of said gate lines to eliminate references to that gate line that causes that defective memory cell to couple a data value to one of said data lines.
33 . The apparatus of claim 32 , wherein said controller tests said memory cells periodically to determine if any of said memory cells is defective and wherein said controller eliminates references in said address assignments to gate lines that cause said detected defective memory cells to couple data values to said data lines.
34 . The apparatus of claim 32 , further comprising programmable logic to prevent the use of data values from data lines when gate lines cause said detected defective memory cells to couple data values to said data lines.
35 . The apparatus of claim 32 , wherein said memory cells are arranged within physical space in a physical order and are arranged within an address space in a logical order, wherein said physical order of at least one memory cell is different than the logical order of that memory cell.
36 . The apparatus of claim 32 , wherein external testing of the controller portion of the apparatus together with testing by the controller of the memory cells achieves a functional testing of a preponderance of the memory cells.
37 . The apparatus of claim 32 , wherein testing by the controller of the memory cells substantially reduces or eliminates the need for external testing of the memory cells of the memory circuit layers.
38 . The apparatus of claim 32 , wherein altering said address assignments comprises preventing the use of at least one defective gate line and replacing references to memory cells addressed using said defective gate line with references to spare memory cells addressed using a spare gate line.
39 . The apparatus of claim 15 , wherein the logic layer and the memory layer are formed with one of single crystal semiconductor material and polycrystalline semiconductor material.
40 . The apparatus of claim 15 , wherein one of the logic layer and the memory layer is formed using a different process technology than another of the logic layer and the memory layer, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.
41 . The apparatus of claim 15 , wherein at least one of the logic and the memory layers comprises a microprocessor.
42 . The apparatus of claim 15 , wherein the logic layer performs testing of the at least one memory layer.
43 . The apparatus of claim 15 , wherein the at least one memory layer has multiple memory locations having at least one memory location used for sparing, wherein data from the at least one memory location on the at least one memory layer is used instead of data from a defective memory location on the at least one memory layer.
44 . The apparatus of claim 15 , wherein the logic layer performs programmable gate line address assignment with respect to the at least one memory layer.
45 . The apparatus of claim 15 , wherein a plurality of interior vertical interconnections traverse at least one of the layers.
46 . The apparatus of claim 15 , wherein continuous vertical interconnections connect circuitry of the layers.
47 . The apparatus of claim 15 , wherein information processing is performed on data routed between circuitry on two or more of the layers.
48 . The apparatus of claim 15 , wherein at least one of the layers has reconfiguration circuitry.
49 . The apparatus of claim 15 , further comprising at least one logic layer having logic for performing at least one of the following functions: virtual memory management, ECC, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing.
50 . The apparatus of claim 15 , further comprising:
a memory array including a plurality of memory cells, a plurality of data lines, and a plurality of gate lines, each memory storage cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to a gate control signal on one of said gate lines;
circuitry for generating a gate control signal in response to an address, including means for mapping addresses to gate lines; and
a controller for determining that one of said memory cells is defective and for altering said mapping to eliminate references to said one of said memory cells.
51 . The apparatus of claim 15 , further comprising:
one or more controller layers;
one or more memory layers;
a plurality of data lines and a plurality of gate lines on each memory layer;
an array of memory cells on each memory layer, each memory cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to the selection of one of said gate lines;
a gate line selection circuit for enabling a gate line for a memory operation, said gate line selection circuit comprising programmable gates to receive address assignments for one or more of said gate lines, said address assignments for determining which of said gate lines is selected for each programmed address assignment; and
controller logic for determining that one of said array memory cells is defective and for altering, in at least one instance, said address assignments of said gate lines to eliminate references to that gate line that causes that defective memory cell to couple a data value to one of said data lines.
52 . The apparatus of claim 51 , wherein said controller tests said memory cells periodically to determine if any of said memory cells is defective and wherein said controller eliminates references in said address assignments to gate lines that cause said detected defective memory cells to couple data values to said data lines.
53 . The apparatus of claim 51 , further comprising programmable logic to prevent the use of data values from data lines when gate lines cause said detected defective memory cells to couple data values to said data lines.
54 . The apparatus of claim 51 , wherein said memory cells are arranged within physical space in a physical order and are arranged within an address space in a logical order, wherein said physical order of at least one memory cell is different than the logical order of that memory cell.
55 . The apparatus of claim 51 , wherein external testing of the controller portion of the apparatus together with testing by the controller of the memory cells achieves a functional testing of a preponderance of the memory cells.
56 . The apparatus of claim 51 , wherein testing by the controller of the memory cells substantially reduces or eliminates the need for external testing of the memory cells of the memory circuit layers.
57 . The apparatus of claim 51 , wherein altering said address assignments comprises preventing the use of at least one defective gate line and replacing references to memory cells addressed using said defective gate line with references to spare memory cells addressed using a spare gate line.
58 . The apparatus of claim 1 , wherein the data source is fabricated using one process technology, and the data sink is fabricated using a different process technology.
59 . The apparatus of claim 15 , wherein the data source layer is fabricated using one process technology, and data sink layer is fabricated using a different process technology.
60 . The apparatus of claim 1 , wherein at least one of the layers has a thickness of one of 10 microns or less and 50 microns or less.
61 . The apparatus of claim 1 , wherein at least one of the layers is formed with a low stress dielectric, wherein the low stress dielectric is at least one of a silicon dioxide dielectric and an oxide of silicon dielectric and is caused to have a tensile stress of about 5×10 8 dynes/cm 2 or less.
62 . The apparatus of claim 15 , wherein at least one of the layers has a thickness of one of 10 microns or less and 50 microns or less.
63 . The apparatus of claim 15 , wherein at least one of the layers is formed with a low stress dielectric, wherein the low stress dielectric is at least one of a silicon dioxide dielectric and an oxide of silicon dielectric and is caused to have a tensile stress of about 5×10 8 dynes/cm 2 or less.