DC-DC conversion device with digitally controlled comparator

1. A DC-DC conversion device, comprising:

a control signal generator to generate a control signal according to a delay signal;

a conversion module coupled to the control signal generator for converting an input voltage into an output voltage according to the control signal; and

a comparison module coupled to the control signal generator and the conversion module for comparing an output voltage of the DC-DC conversion device with a reference voltage to generate a comparison result and outputting the delay signal according to the comparison result, an enable signal and a clock signal, wherein the comparison module comprises:

a voltage divider coupled to the conversion module and the comparison module to generate a divided voltage by dividing the output voltage, wherein the voltage divider comprises:

a first resistor having a first terminal coupled to the conversion module and a second terminal coupled to the comparison module; and

a second resistor having a first terminal coupled to the second terminal of the first resistor, and a grounded second terminal, wherein the first resistor and the second resistor divide the output voltage to generate and input the divided voltage to the comparison module

a comparison unit coupled to the voltage divider for comparing the reference voltage and the divided voltage resulted from the voltage divider to generate a comparison signal; and

at least one delay unit coupled to the comparison unit and the control signal generator to generate the delay signal according to the comparison signal, the enable signal and the clock signal, wherein the delay unit comprises:

a control circuit for generating a clock input signal and a reset signal according to the comparison signal, the enable signal and the clock signal, wherein the control circuit comprises:

a NAND gate for executing a NAND operation on the enable signal and the comparison signal to generate a first operation signal;

a second computing unit coupled to the first computing unit for executing a second logic operation on the clock signal and the first operation signal to generate a second operation signal;

a first processing unit coupled to the first computing unit for processing the first operation signal to generate the reset signal; and

a second processing unit coupled to the second computing unit for processing the second operation signal to generate the clock input signal; and

a processing circuit coupled to the control circuit for generating the delay signal according to the clock input signal and the reset signal.

2. The device as claimed in claim 1 , wherein the second computing unit is a NOR gate, the second logic operation is a NOR operation, and the second computing unit executes the NOR operation on the clock signal and the first operation signal to generate the second operation signal.

3. The device as claimed in claim 2 , wherein the first processing unit and the second processing unit are inverters.

4. The device as claimed in claim 3 , wherein the delay unit includes a flip flop.

5. The device as claimed in claim 1 , wherein the first processing unit inverts the first operation signal to generate the reset signal, and the second processing unit inverts the second operation signal to generate the clock input signal.

6. The device as claimed in claim 1 , wherein the processing circuit comprises:

at least one delay unit coupled to a first processing unit, a second processing unit and the control signal generator for delaying the clock input signal to generate the delay signal according to the reset signal.

7. The device as claimed in claim 1 , wherein the comparison module includes a comparator.

8. The device as claimed in claim 1 , wherein the conversion module is a voltage converter.

9. The device as claimed in claim 1 , wherein the conversion module is a DC to DC converter.

10. A voltage conversion method, comprising:

(a) providing a control signal for controlling a voltage conversion operation;

(b) converting an input voltage into an output voltage according to the control signal;

(c) comparing the output voltage with a reference voltage to generate a comparison signal, wherein the step (c) further comprises:

(c1) voltage-dividing the output voltage to generate a divided voltage; and

(c2) comparing the reference voltage with the divided voltage to generate the comparison signal;

(d) generating a delay signal according to an enable signal, a clock signal and the comparison signal wherein the step (d) further comprises:

(d1) generating a clock input signal and a reset signal according to the enable signal, the clock signal and the comparison signal, wherein the step (d1) further comprises:

(d11) executing a NAND operation on the enable signal and the comparison signal to generate a first operation signal;

(d12) executing a second logic operation on the clock signal and the first operation signal to generate a second operation signal;

(d13) processing the first operation signal to generate the reset signal; and

(d14) processing the second operation signal to generate the clock input signal; and

(d2) generating the delay signal according to the clock input signal and the reset signal; and

(e) adjusting the time for the voltage conversion operation according to the control signal and the delay signal.

11. The method as claimed in claim 10 , wherein the step (d12) executes the NOR operation on the clock signal and the first operation signal to generate the second operation signal.

12. The method as claimed in claim 11 , wherein the step (s14) inverts the second operation signal to generate the clock input signal.

13. The method as claimed in claim 10 , wherein the step (d13) inverts the first operation signal to generate the reset signal.

14. The method as claimed in claim 10 , wherein the step (d2) further comprises:

(d21) delaying the clock input signal to generate the delay signal according to the reset signal.