Memory cell with proportional current self-reference sensing
View Patent ↗Various embodiments of the present invention are generally directed to a method and apparatus for sensing a programmed state of a memory cell, such as a spin-torque transfer random access memory (STRAM) cell. A first read current is applied to the memory cell to generate a first voltage. A second read current is subsequently applied to the memory cell to generate a second voltage, with the second read current being proportional in magnitude to the first read current. A comparison is made between the first and second voltages to determine the programmed state of the memory cell.
1. A method comprising:
applying a first read current to a memory cell to generate a first voltage;
subsequently applying a second read current to the memory cell to generate a second voltage, wherein the second voltage is generated in relation to a voltage divider comprising first and second resistors with corresponding first and second resistances, the second read current having a magnitude selected in relation to a ratio of said first and second resistances; and
comparing the first and second voltages to determine a programmed state of the memory cell.
2. The method of claim 1 , wherein the memory cell comprises a magnetic tunneling junction (MTJ) selectively programmable between a low resistance state and a high resistance state.
3. The method of claim 1 , wherein the applying step comprises storing the first voltage on a first capacitor, and wherein the subsequently applying step comprises storing the second voltage on a second capacitor.
4. The method of claim 1 , wherein the comparing step comprises applying the respective first and second voltages to respective input terminals of a sense amplifier.
5. The method of claim 1 , wherein the respective first and second voltages generated during the applying and subsequently applying steps have magnitudes in relation to respective voltage drops across the memory cell from the application of the respective first and second read currents.
6. The method of claim 1 , wherein a programmable current driver is used to sequentially output the first and second read currents.
7. The method of claim 1 , wherein the voltage divider is connected in parallel with the memory cell, the second voltage is obtained from a node between the first and second resistors, and the magnitude of the second read current is predetermined in relation to a ratio of the second resistance to a sum of the first and second resistances.
8. The method of claim 1 , wherein the comparing step comprises using a first stage cross-coupled differential sense amplifier to initially sense a voltage differential between the first and second voltages, and then using a second stage sense amplifier coupled to the first stage cross-coupled differential sense amplifier to output a bit value with a logic level corresponding to a programmed state of the memory cell.
9. The method of claim 1 , wherein the memory cell is alternately programmable to a low resistance state and a high resistance state, respectively, wherein the first voltage is substantially equal to the second voltage when the memory cell is programmed to the low resistance state, and wherein the first voltage is substantially greater than the second voltage when the memory cell is programmed to the high resistance state.
10. An apparatus comprising:
a memory cell;
a voltage divider coupled to the memory cell comprising first and second resistors with corresponding first and second resistances;
a first current driver circuit configured to apply a first read current to the memory cell to generate a first voltage;
a second current driver circuit configured to subsequently apply a second read current to the memory cell to generate a second voltage, wherein the second read current has a magnitude proportional to the first read current and established in relation to the first and second resistances of the voltage divider; and
a sense circuit configured to compare the first and second voltages to determine a programmed state of the memory cell.
11. The apparatus of claim 10 , wherein the memory cell comprises a magnetic tunneling junction (MTJ) selectively programmable between a low resistance state and a high resistance state.
12. The apparatus of claim 10 , further comprising first and second capacitors coupled to the memory cell and to the sense circuit, wherein the first voltage is stored on the first capacitor and the second voltage is stored on the second capacitor.
13. The apparatus of claim 10 , wherein the respective first and second voltages have magnitudes in relation to respective voltage drops across the memory cell from the respective first and second read currents.
14. The apparatus of claim 10 , wherein the first and second current driver circuits constitute a single programmable current driver used to sequentially output the first and second read currents responsive to respective current output enable signals.
15. The apparatus of claim 10 , wherein the sense circuit comprises a first stage cross-coupled differential sense amplifier configured to initially sense a voltage differential between the first and second voltages, and a second stage operational amplifier coupled to the first stage cross-coupled differential sense amplifier and configured to output a bit value with a logic level corresponding to a programmed state of the memory cell.
16. The apparatus of claim 10 , wherein the memory cell is alternately programmable to a low resistance state and a high resistance state, respectively, wherein the first voltage is substantially equal to the second voltage when the memory cell is programmed to the low resistance state, and wherein the first voltage is substantially greater than the second voltage when the memory cell is programmed to the high resistance state.
17. A non-volatile memory device comprising:
an array of spin-torque transfer random access memory (STRAM) cells;
a voltage divider coupled to a selected STRAM cell from said array, the voltage divider comprising first and second resistors;
a driver circuit which sequentially applies first and second read currents to the selected STRAM cell during a read operation to generate respective first and second voltages, wherein the second voltage is obtained from a node between the first and second resistors, and a magnitude of the second read current is determined in relation to the first and second resistances; and
a sense circuit which determines a programmed state of the selected STRAM cell in relation to the first and second voltages.
18. The memory device of claim 17 , further comprising first and second capacitors coupled to the selected STRAM cell and to the sense circuit, wherein the first voltage is stored on the first capacitor and the second voltage is stored on the second capacitor.
19. The memory device of claim 18 , wherein the first and second resistors are connected in series with said node therebetween, and the second capacitor is connected to said node.
20. The memory device of claim 17 , wherein the respective first and second voltages have magnitudes in relation to respective voltage drops across the selected STRAM cell from the respective first and second read currents.