Sample-and-hold circuit and CCD image sensor
View Patent ↗Noise is more effectively reduced in one circuit. When sampling and holding is performed, switching of an ON resistance of MOS transistors (MSH 1 and MSH 2 ) that are for sampling is made in two or more stages according to speed of sampling. Here, a level adjustment circuit ( 20 ) is provided that generates sample-and-hold pulse signals (φSH 1 S and φSH 2 S), which vary voltage to enable switching the ON resistance of the MOS transistors (MSH 1 and MSH 2 ), to be provided to gates of the MOS transistors (MSH 1 and MSH 2 ).
1. A sample-and-hold circuit, comprising:
a switch element for performing sampling and holding an input signal, a magnitude of an ON resistance of the switch element in a sampling mode being set in accordance with a speed at which the input signal is sampled; and
a level adjustment circuit which generates a sample-and-hold pulse signal to be provided to a gate of said switch element, the sample-and-hold pulse signal varying in voltage being based on the sampling speed to control the magnitude of the ON resistance of said switch element.
2. The sample-and-hold circuit according to claim 1 , wherein said switch element is a MOS transistor.
3. The sample-and-hold circuit according to claim 2 , further comprising:
at least one additional MOS transistor,
wherein said level adjustment circuit individually controls a gate voltage of each of said MOS transistors.
4. The sample-and-hold circuit according to claim 3 , wherein said level adjustment circuit generates said sample-and-hold pulse signal with an amplitude and a level each corresponding to a speed classification of sampling.
5. The sample-and-hold circuit according to claim 1 , wherein said level adjustment circuit generates said sample-and-hold pulse signal with an amplitude and a level each corresponding to a speed classification of sampling.
6. The sample-and-hold circuit according to claim 5 ,
wherein said level adjustment circuit performs a level shift of each of a first and a second timing pulse signal, and
wherein, with said sample-and-hold pulse signal having the amplitude attenuated or unchanged, said level adjustment circuit enables variation of any of a i) level shift amount and ii) an amplitude attenuation amount of said sample-and-hold pulse signal in accordance with the speed classification of sampling.
7. The sample-and-hold circuit according to claim 6 , wherein said level adjustment circuit performs setting such that said first and said second timing pulse signals are identical signals.
8. The sample-and-hold circuit according to claim 6 , wherein said level adjustment circuit performs setting such that said first and said second timing pulse signals are signals of different pulse widths made active at a same timing.
9. A CCD image sensor, comprising:
a CCD, including a sample-and-hold circuit according to claim 1 configured to sample and hold an output signal of said CCD.
10. A sample-and-hold circuit, comprising:
means for switching in two or more stages a magnitude of an ON resistance of a switch element for sampling an input signal at a predetermined sampling speed, the magnitude being switched according to the sampling speed,
said means for switching comprises level adjustment means for generating a sample-and-hold pulse signal which varies a voltage to be provided to a gate of said switching means and controls the magnitude of the ON resistance of said switching means.
11. The sample-and-hold circuit according to claim 10 , wherein said switch element comprises a MOS transistor.
12. The sample-and-hold circuit according to claim 11 , further comprising:
at least one additional MOS transistor,
wherein said level adjustment means individually controls a gate voltage of each of said MOS transistors.
13. The sample-and-hold circuit according to claim 10 , wherein said sample-and-hold pulse signal has an amplitude and a level each corresponding to a speed classification of sampling.
14. The sample-and-hold circuit according to claim 13 ,
wherein said level adjustment means performs a level shift of each of a first and a second timing pulse signal, and
wherein, with said sample-and-hold pulse signal having the amplitude attenuated or unchanged, enables variation of any of a i) level shift amount and ii) an amplitude attenuation amount of said sample-and-hold pulse signal in accordance with the speed classification of sampling.
15. The sample-and-hold circuit according to claim 14 , wherein said level adjustment means performs setting such that said first and said second timing pulse signals are identical signals.
16. The sample-and-hold circuit according to claim 14 , wherein said level adjustment means performs setting such that said first and said second timing pulse signals are signals of different pulse widths made active at a same timing.
17. A CCD image sensor, comprising:
a CCD, including a sample-and-hold circuit according to claim 10 configured to sample and hold an output signal of said CCD.