Semiconductor memory devices having vertically-stacked transistors therein

1. An integrated circuit memory device, comprising:

an array of memory cells electrically coupled to a plurality of word lines, said array comprising memory cell transistors having channel regions formed in corresponding first semiconductor regions; and

a word line decoder having a plurality of drivers therein electrically coupled to the plurality of word lines, said plurality of drivers comprising driver transistors having channel regions formed in corresponding second semiconductor regions that are displaced vertically relative to the first semiconductor regions;

wherein the memory cells in said array are static random access memory (SRAM) cells having P-type and N-type memory transistors therein; and

wherein the P-type and N-type memory transistors are formed in the first and second semiconductor regions, respectively, or vice versa.

2. The memory device of claim 1 , wherein the first semiconductor regions are disposed within a semiconductor substrate; and wherein the second semiconductor regions are disposed in semiconductor layers that are displaced vertically relative to the semiconductor substrate.

3. The memory device of claim 1 , wherein the second semiconductor regions are disposed within a semiconductor substrate; and wherein the first semiconductor regions are disposed in semiconductor layers that are displaced vertically relative to the semiconductor substrate.

4. The memory device of claim 1 , wherein the driver transistors comprise P-type and N-type driver transistors formed in the first and second semiconductor regions, respectively, or vice versa.

5. A semiconductor memory device having transistors of stacked structure, comprising:

a memory cell array block which includes a plurality of word lines and a plurality of memory cells which each includes at least one first transistor connected between the plurality of word lines; and

a word line decoder which includes a plurality of drivers which drive the plurality of word lines, respectively;

wherein the plurality of word lines are disposed on at least one first layer, and the plurality of drivers are disposed on at least one second layer different from the first layer; and

wherein the plurality of memory cells are static memory cells that respectively comprise two second transistors, the first transistor is disposed on the first layer, and the second transistors are disposed on at least one of the first layer and the second layer.

6. The semiconductor memory device of claim 5 , wherein each of the plurality of drivers comprises at least two transistors.

7. A semiconductor memory device, comprising:

a memory cell array block containing a plurality of word lines and a plurality of memory cells that respectively include at least one first transistor connected between the plurality of word lines; and

a word line decoder comprises a plurality of drivers which drive the plurality of word lines, respectively;

wherein the plurality of word lines are disposed on at least one first layer, and the plurality of drivers are disposed on at least one second layer different from the first layer; and

wherein the at least one second layer includes two second layers, and the plurality of drivers are disposed on the two second layers.

8. The semiconductor memory device of claim 7 , wherein each of the plurality of drivers comprises at least two second transistors, and the at least two second transistors of each of the plurality of drivers are disposed on the same layer of the at least two second layers.

9. The semiconductor memory device of claim 7 , wherein the plurality of memory cells are static memory cells, the static memory cell further comprises two second transistors, the first transistor is disposed on the first layer, and the second transistors are disposed on at least one of the first layer and the second layer.

10. The semiconductor memory device of claim 7 , wherein the plurality of memory cells are non-volatile memory cells, and the first transistor is disposed on the first layer.

11. A semiconductor memory device, comprising:

a memory cell array block containing a plurality of word lines and a plurality of memory cells that respectively include at least one first transistor connected between the plurality of word lines; and

a word line decoder comprising a plurality of drivers that drive the plurality of word lines, respectively;

wherein the plurality of word lines are disposed on at least one first layer, and the plurality of drivers are disposed on at least one second layer different from the first layer; and

wherein the at least one first layer includes two first layers, and the plurality of word lines are disposed on the two first layers.

12. A semiconductor memory device, comprising:

a memory cell array block which includes a plurality of word lines and a plurality of memory cells which each includes at least one first transistor connected between the plurality of word lines; and

a word line decoder which includes a plurality of drivers which drive the plurality of word lines, respectively;

wherein the plurality of word lines are dispersed and stacked on at least two layers, and the plurality of drivers connected to the plurality of word lines are disposed on a corresponding layer of the at least two layers; and

wherein the plurality of memory cells are static memory cells that respectively comprise two second transistors, and the first transistor and the second transistors are disposed on at least one of the at least two layers.

13. The semiconductor memory device of claim 12 , wherein each of the plurality of drivers comprises at least two transistors.

14. The semiconductor memory device of claim 12 , wherein the plurality of memory cells are non-volatile memory cells, and the first transistor is disposed on the first layer.