Nonvolatile semiconductor memory device
View Patent ↗A nonvolatile semiconductor memory device comprises a memory cell array including first and second mutually crossing lines and electrically erasable programmable memory cells arranged at intersections of the first and second lines, each memory cell containing a variable resistor operative to nonvolatilely store the resistance thereof as data and a first non-ohmic element operative to switch the variable resistor; and a clamp voltage generator circuit operative to generate a clamp voltage required for access to the memory cell and applied to the first and second lines. The clamp voltage generator circuit has a temperature compensation function of compensating for the temperature characteristic of the first non-ohmic element.
1. A nonvolatile semiconductor memory device, comprising:
a memory cell array including first and second mutually crossing lines and electrically erasable programmable memory cells arranged at intersections of said first and second lines, each memory cell containing a variable resistor operative to nonvolatilely store the resistance thereof as data and a first non-ohmic element operative to switch said variable resistor; and
a clamp voltage generator circuit operative to generate a clamp voltage required for access to said memory cell and applied to said first and second lines,
wherein said clamp voltage generator circuit has a temperature compensation function of compensating for the temperature characteristic of said first non-ohmic element.
2. The nonvolatile semiconductor memory device according to claim 1 , wherein said clamp voltage generator circuit includes a second non-ohmic element operative to compensate for the temperature characteristic of said first non-ohmic element.
3. The nonvolatile semiconductor memory device according to claim 2 , further comprising a sense amplifier connected to said first or second line via a clamp transistor having a gate supplied with said clamp voltage and operative to read out data from said memory cell,
wherein said clamp voltage generator circuit includes a diode-connected transistor provided close to the output node for providing said clamp voltage.
4. The nonvolatile semiconductor memory device according to claim 2 , wherein said first non-ohmic element and said second non-ohmic element have an equal characteristic.
5. The nonvolatile semiconductor memory device according to claim 2 , wherein said memory cell array has a multilayered structure,
said first non-ohmic element and said second non-ohmic element are formed in the same layer.
6. The nonvolatile semiconductor memory device according to claim 3 , wherein said clamp transistor and said diode-connected transistor have an equal characteristic.
7. The nonvolatile semiconductor memory device according to claim 3 , wherein said clamp voltage generator circuit includes a variable resistor circuit operative to generate a voltage applied to said variable resistor on access to said memory cell.
8. The nonvolatile semiconductor memory device according to claim 7 , wherein said clamp voltage generator circuit includes a serial circuit containing said diode-connected transistor, said second non-ohmic element and said variable resistor circuit, serially connected between said output node for providing said clamp voltage and a reference node.
9. The nonvolatile semiconductor memory device according to claim 8 , wherein said clamp voltage generator circuit includes a constant current circuit operative to supply a constant current to said serial circuit.
10. The nonvolatile semiconductor memory device according to claim 8 , wherein said clamp voltage generator circuit includes a constant voltage circuit operative to control said reference node at a constant voltage.
11. A nonvolatile semiconductor memory device, comprising:
a memory cell array including first and second mutually crossing lines and electrically erasable programmable memory cells arranged at intersections of said first and second lines, each memory cell containing a variable resistor operative to nonvolatilely store the resistance thereof as data and a first non-ohmic element operative to switch said variable resistor;
a sense amplifier containing a clamp transistor operative to clamp a voltage required for access to said memory cell and applied to said first or second line; and
a clamp voltage generator circuit operative to generate a clamp voltage to control said clamp transistor,
wherein said clamp voltage generator circuit includes a variable resistor circuit operative to set a voltage applied to said variable resistor on access to said memory cell, and a second non-ohmic element operative to compensate for the temperature characteristic of said first non-ohmic element.
12. The nonvolatile semiconductor memory device according to claim 11 , wherein said clamp voltage generator circuit includes a diode-connected transistor provided close to the output node for providing said clamp voltage.
13. The nonvolatile semiconductor memory device according to claim 11 , wherein said first non-ohmic element and said second non-ohmic element have an equal characteristic.
14. The nonvolatile semiconductor memory device according to claim 11 , wherein said memory cell array has a multilayered structure,
said first non-ohmic element and said second non-ohmic element are formed in the same layer.
15. The nonvolatile semiconductor memory device according to claim 12 , wherein said clamp voltage generator circuit includes a plurality of such second non-ohmic elements connected in parallel with each other, and a plurality of such diode-connected transistors connected in parallel with each other and in series with said second non-ohmic elements.
16. The nonvolatile semiconductor memory device according to claim 12 , wherein said clamp voltage generator circuit includes a constant current circuit operative to supply a constant current to said variable resistor circuit via said diode-connected transistor and said second non-ohmic element in said clamp voltage generator circuit.
17. A nonvolatile semiconductor memory device, comprising:
a memory cell array of a multilayered structure including first and second mutually crossing lines and electrically erasable programmable memory cells arranged at intersections of said first and second lines, each memory cell containing a variable resistor operative to nonvolatilely store the resistance thereof as data and a first non-ohmic element operative to switch said variable resistor; and
a clamp voltage generator circuit operative to generate a clamp voltage required for access to said memory cell and applied to said first and second lines,
wherein said clamp voltage generator circuit includes a second non-ohmic element operative to compensate for the temperature characteristic of said first non-ohmic element, said second non-ohmic element is formed in the same layer as that of said memory cell accessible with said clamp voltage generation.
18. The nonvolatile semiconductor memory device according to claim 17 , further comprising a sense amplifier circuit connected to said first or second line via a clamp transistor having a gate supplied with said clamp voltage and operative to read out data from said memory cell,
wherein said clamp voltage generator circuit includes a diode-connected transistor provided close to the output node for providing said clamp voltage.
19. The nonvolatile semiconductor memory device according to claim 17 , wherein said first non-ohmic element and said second non-ohmic element have an equal characteristic.
20. The nonvolatile semiconductor memory device according to claim 17 , wherein said clamp voltage generator circuit includes a variable resistor circuit operative to generate a voltage applied to said variable resistor on access to said memory cell.