MEMORY SYSTEMS WITH A PLURALITY OF STRUCTURES AND METHODS FOR OPERATING THE SAME
Memory systems, such as solid state drives, and methods of operating such memory systems are disclosed, such as those adapted to provide parallel processing of data using redundant array techniques. Individual flash devices or channels containing multiple flash devices are operated as individual drives in an array of redundant drives. Ranges of physical addresses corresponding to logical addresses are provided to a host for performing read and write operations on different channels, such as to improve read variability.
1 . A method for operating a memory system having a plurality of physical structures, the method comprising:
routing write operations for the memory system on a first subset of the plurality of physical structures; and
routing read operations for the memory system on a second subset of the plurality of physical structures different from the first subset of the plurality of physical structures when write operations are routed to the first subset of the plurality of physical structures.
2 . The method of claim 1 , wherein the plurality of physical structures are operated in parallel.
3 . The method of claim 2 , wherein routing write operations and routing read operations are performed by a redundant array controller.
4 . The method of claim 3 , wherein the redundant array controller includes a table having information on a logical to physical relationship between logical memory locations provided to the redundant array controller and physical memory locations corresponding to the plurality of physical structures, a respective set of logical memory locations corresponding to each physical structure.
5 . The method of claim 1 , and further comprising:
controlling the routing using a redundant array controller, wherein each of the plurality of channels comprises an individual drive in a redundant array.
6 . The method of claim 5 , wherein a plurality of redundant array controllers are used, each controller operating as an individual drive in a master redundant array.
7 . The method of claim 1 , wherein the physical structures are channels.
8 . The method of claim 1 , wherein write operations are routed to the memory system on the basis of bandwidth available on the first subset of the plurality of physical structures.
9 . The method of claim 1 , wherein each of the plurality of physical structures in the memory system is established as a separate drive partition for an operating system.
10 . The method of claim 1 , wherein each of the plurality of physical structures in the memory system is established as a separate drive partition for a driver for the memory system.
11 . A method for operating a memory system, the method comprising:
assigning each channel of a plurality of channels of the memory system to a range of logical addresses;
storing information corresponding to the assignment of logical addresses;
providing a host the ranges of logical addresses corresponding to each of the plurality of channels; and
operating the solid state drive channels as individual drives in an array of redundant drives.
12 . The method of claim 11 , wherein operating the channels as individual drives in an array of redundant drives further comprises:
controlling routing of read operations to the memory system with a controller.
13 . The method of claim 12 , wherein controlling routing further comprises:
routing write operations for the memory system to a first subset of the plurality of channels; and
routing read operations to the memory system on a second subset of the plurality of channels different from the first subset of the plurality of channels when write operations are routed to the first subset of the plurality of channels.
14 . A method of operating a memory system having an array of drives, comprising:
assigning each of a plurality of individual channels of a smemory system as an individual drive in the array;
storing information corresponding to a range of logical addresses corresponding to a range of physical addresses for each of the plurality of channels;
providing a host the stored information; and
controlling the plurality of individual channels.
15 . The method of claim 14 , wherein controlling further comprises:
routing read and write operations to different channels of the array to reduce read variability.
16 . The method of claim 15 , wherein routing further comprises:
routing write operations for the memory system to a first subset of the plurality of channels when a second subset of the plurality of channels different than the first subset is routed read operations.
17 . The method of claim 16 , wherein the second subset of the plurality of channels is exclusive of the first subset of the plurality of channels.
18 . The method of claim 14 , wherein a plurality of arrays are connected to a master array, and further comprising:
operating each of the plurality of arrays as an individual drive in a master array.
19 . A memory system, comprising:
a plurality of channels, each channel being coupled to at least one solid state device;
a first subset of the plurality of channels, the first subset dedicated at a particular time to read operations; and
a second subset of the plurality of channels, the second subset being different than the first subset and dedicated at the particular time to non-read operations.
20 . The memory system of claim 19 , and further comprising:
a first redundant array controller, the controller connected to the plurality of channels, each channel operating as a drive in a redundant array of drives; and
a logical block address (LBA) table, the LBA table containing mapping information of physical addresses corresponding to individual channels of the plurality of channels and of logical addresses corresponding to the individual channels.
21 . The memory system of claim 20 , wherein each channel further comprises a plurality of flash devices connected thereto, each flash device of the plurality of flash devices connected to a respective channel operating in parallel thereon.
22 . The memory system of claim 21 , wherein the controller is one of a plurality of additional redundant array controllers, each connected in parallel with each other, each of the plurality of additional redundant array controllers comprising:
a plurality of channels, each channel being coupled to at least one solid state device; and
a logical block address (LBA) table, the LBA table containing mapping information of physical addresses corresponding to individual channels of the plurality of channels and of logical addresses corresponding to the individual channels; and
a master array controller connected to the plurality of additional redundant array controllers, each of the plurality of additional redundant array controllers operating as an individual drive in a master array.
23 . A memory system, comprising:
a controller for controlling operation of an array of a plurality of channels of the memory system, wherein the controller is adapted to assign channels of the memory system to particular operations, the controller comprising:
a table having mapping information of logical addresses corresponding to physical channels of the memory system; and
a plurality of channel connections to the plurality of channels; and
at least one flash memory device, each of the at least one flash memory devices connected to one of the plurality of channels of the memory system, and each channel of the memory system connected to the controller.
24 . The memory system of claim 23 , wherein the controller further comprises a redundant array controller, and wherein each channel of the memory system is operated as a drive in the array.
25 . The memory system of claim 23 , wherein the table further includes mapping information of logical addresses corresponding to the at least one flash memory device;
wherein the controller further comprises a redundant array controller; and
wherein each flash device of the memory system is operated as a drive in a redundant array.
26 . The memory system of claim 23 , wherein each channel of the solid state drive has a plurality of logical addresses corresponding to the physical addresses of the plurality of flash devices connected to its respective channel, and wherein the controller is a redundant array controller capable of operating each respective channel as an individual drive in an array of redundant drives.
27 . The memory system of claim 23 , wherein the table is a logical block address table.
28 . A redundant array of drives, comprising:
a controller; and
a plurality of individual solid state drives, each solid state drive coupled to the controller, and comprising:
a controller for controlling operation of an array of a plurality of channels of the solid state drive, wherein the controller is adapted to assign channels of the solid state drive to particular operations, the controller comprising:
a table having mapping information of logical addresses corresponding to physical channels of the solid state drive; and
a plurality of channel connections to the plurality of channels; and
at least one flash memory device, each of the at least one flash memory devices connected to one of the plurality of channels of the solid state drive, and each channel of the solid state connected to the controller.