Multiple thickness and/or composition high-K gate dielectrics and methods of making thereof

1. A method of making an integrated circuit with at least one of multiple thickness high-K gate dielectric layers or multiple composition high-K gate dielectric layers, comprising:

forming a conventional gate dielectric layer having a first thickness in a first portion of a substrate and a second thickness in a second portion of the substrate, the first thickness greater than the second thickness;

forming a layer of high-K atoms over the conventional gate dielectric;

heating the layer of high-K atoms, the conventional gate dielectric layer, and the substrate to form a high-K gate dielectric layer, the high-K gate dielectric layer having at least one of a first thickness or a first composition in the first portion and at least one of a second thickness or a second composition in the second portion, the first thickness greater than the second thickness.

2. The method of claim 1 , further comprising:

forming a first set of transistors in the first portion of the substrate and a second set of transistors in the second portion of the substrate, the first set of transistors comprising a high-K gate dielectric of at least one a first thickness or a first composition and the second set of transistors comprising a high-K gate dielectric of at least one of a second thickness or a second composition, the first thickness greater than the second thickness and the first composition different from the second composition.

3. The method of claim 1 , wherein forming the layer of high-K atoms comprises sputtering, physical vapor deposition, evaporative deposition, electron beam physical vapor deposition, cathodic arc deposition, or pulsed laser deposition.

4. The method of claim 1 , wherein heating is conducted at a temperature from about 800° C. to about 1200° C. for a time from about 1 second to about 5 minutes.

5. The method of claim 1 , wherein forming the layer of high-K atoms comprises sputtering one or more of zirconium, hafnium, lanthanum, or gadolinium.

6. The method of claim 1 , wherein heating is conducted in an atmosphere of one or more of nitrogen, helium, neon, argon, xenon, or oxygen.

7. The method of claim 2 , wherein the first thickness of the high-K gate dielectric of the first set of transistors is about 0.1 nm greater than the second thickness of the high-K gate dielectric of the second set of transistors.

8. A method of making an integrated circuit with multiple thickness high-K gate dielectric layers, comprising:

forming a conventional gate dielectric layer having a first thickness in a first portion of a substrate, a second thickness in a second portion of the substrate, and a third thickness in a third portion of the substrate, the first thickness greater than the second thickness and the second thickness greater than the third thickness;

forming a layer of high-K atoms over the conventional gate dielectric;

heating the layer of high-K atoms, the conventional gate dielectric layer, and the substrate to form a high-K gate dielectric layer, the high-K gate dielectric layer having a first thickness in the first portion, a second thickness in the second portion, and a third thickness in the third portion, the first thickness greater than the second thickness and the second thickness greater than the third thickness.

9. The method of claim 8 further comprising:

forming a first set of transistors in the first portion of the substrate, a second set of transistors in the second portion of the substrate, and a third set of transistors in the third portion of the substrate, the first set of transistors comprising a high-K gate dielectric of a first thickness, the second set of transistors comprising a high-K gate dielectric of a second thickness, and the third set of transistors comprising a high-K gate dielectric of a third thickness, the first thickness greater than the second thickness and the second thickness greater than the third thickness.

10. The method of claim 8 , wherein forming the layer of high-K atoms comprises sputtering one or more of zirconium, hafnium, lanthanum, or gadolinium.

11. The method of claim 8 , wherein heating is conducted at a temperature from about 850° C. to about 1100° C. for a time from about 5 seconds to about 2 minutes.

12. The method of claim 8 , wherein heating is conducted at a pressure from about 0 atmospheres to about 1.2 atmospheres.

13. The method of claim 8 , wherein the layer of high-K atoms has a thickness from about 0.1 nm to about 25 nm.

14. The method of claim 9 , wherein the first thickness of the high-K gate dielectric of the first set of transistors is about 0.1 nm greater than the second thickness of the high-K gate dielectric of the second set of transistors, and the second thickness of the high-K gate dielectric of the second set of transistors is about 0.1 nm greater than the third thickness of the high-K gate dielectric of the third set of transistors.

15. An integrated circuit, comprising:

a first set of transistors over a first portion of a substrate, a second set of transistors over a second portion of the substrate;

each of the first set of transistors comprising a gate, a high-K gate dielectric, and a conventional gate dielectric and each of the second set of transistors comprising a gate, a high-K gate dielectric, and optionally a conventional gate dielectric;

the first set of transistors comprising a high-K gate dielectric of at least one of a first thickness or a first composition, and the second set of transistors comprising a high-K gate dielectric of at least one of a second thickness or a second composition, the first thickness greater than the second thickness and the first composition different from the second composition;

the high-K gate dielectric of the first set of transistors and the second set of transistors comprises one or more of Hf x Si 1-x O 2 , Hf x Si 1-x ON, Zr x Si 1-x O 2 , Zr x Si 1-x ON, La x Si 1-x O 2 , La x Si 1-x ON, Gd x Si 1-x O 2 , or Gd x Si 1-x ON, where x is between 0 and 1;

a third set of transistors in a third portion of the substrate;

each of the second set of transistors comprising a gate, a high-K gate dielectric, and optionally a conventional gate dielectric; and

the third set of transistors comprising a high-K gate dielectric of a third thickness, the second thickness greater than the third thickness.

16. The integrated circuit of claim 15 , wherein the high-K gate dielectric of the first set of transistors have a thickness from about 0.25 nm to about 20 nm and the high-K gate dielectric of the second set of transistors have a thickness from about 0.25 nm to about 20 nm.

17. The integrated circuit of claim 15 , wherein the high-K gate dielectric of the first set of transistors and the second set of transistors comprises Hf x Si 1-x O 2 or Hf x Si 1-x ON, where x is between 0 and 1; and the first thickness of the high-K gate dielectric of the first set of transistors is at least about 0.25 nm greater than the second thickness of the high-K gate dielectric of the second set of transistors.

18. The integrated circuit of claim 15 , wherein the conventional gate dielectric of the first set of transistors has a first thickness and the conventional gate dielectric of the second set of transistors has a second thickness, the first thickness greater than the second thickness.

19. The integrated circuit of claim 15 , wherein the conventional gate dielectric of the first set of transistors comprises silicon dioxide or silicon oxynitride.

20. The integrated circuit of claim 15 , wherein the integrated circuit is an LSI or a VLSI.

21. A method of suppressing gate leakage current while simultaneously mitigating mobility degradation, comprising using the integrated circuit of claim 15 .