Granted Patent B2

US 7,960,267 · App. 12/414,778 · Granted Jun 14, 2011

Abstract

Claims (73)

1. A method of making a semiconductor device on a semiconductor layer, comprising:

forming a gate dielectric over the semiconductor layer;

forming a layer of gate material over the gate dielectric;

etching the layer of gate material to form a select gate;

forming a storage layer that extends over the select gate and over a portion of the semiconductor layer;

depositing an amorphous silicon layer over the storage layer;

etching the amorphous silicon layer to form a control gate; and

annealing the semiconductor device to crystallize the amorphous silicon layer,

wherein the step of depositing the amorphous silicon layer comprises sputtering silicon and an impurity, wherein the impurity comprises one of group consisting of nickel, gold, aluminum, silver, and palladium.

2. A method of making a semiconductor device on a semiconductor layer, comprising:

forming a gate dielectric over the semiconductor layer;

forming a layer of gate material over the gate dielectric;

etching the layer of gate material to form a select gate;

forming a storage layer that extends over the select gate and over a portion of the semiconductor layer;

depositing an amorphous silicon layer over the storage layer;

etching the amorphous silicon layer to form a control gate;

annealing the semiconductor device to crystallize the amorphous silicon layer; and

forming a capping layer over the semiconductor device, the capping layer formed prior to the step of annealing the semiconductor device.

3. The method of claim 2 , further comprising removing the capping layer from over the semiconductor device after the step of annealing the semiconductor device.

4. The method of claim 2 , wherein forming the capping layer further comprises forming a capping layer that causes a channel region in the semiconductor layer to be laterally tensile stressed.

5. The method of claim 2 , wherein forming the capping layer further comprises forming the capping layer from tensile stressed silicon nitride.

6. The method of claim 1 , wherein annealing the semiconductor device to crystallize the amorphous silicon layer further comprises annealing the semiconductor device at a temperature in a range of 500 to 1100 degrees Celsius.

7. The method of claim 1 , wherein depositing the amorphous silicon layer over the storage layer further comprises depositing the amorphous silicon layer to have a thickness in a range of 50 to 250 nanometers.

8. The method of claim 1 , wherein etching the amorphous silicon layer to form the control gate further comprises etching the amorphous silicon layer to form the control gate having a portion formed over a portion of the select gate.

9. A method of making a semiconductor device on a semiconductor layer, comprising:

forming a gate dielectric over the semiconductor layer;

forming a layer of gate material over the gate dielectric;

etching the layer of gate material to form a select gate;

forming a storage layer that extends over the select gate and over a portion of the semiconductor layer;

depositing an amorphous silicon layer over the storage layer;

etching the amorphous silicon layer to form a control gate; and

annealing the semiconductor device to crystallize the amorphous silicon layer,

wherein forming the storage layer is further characterized by the storage layer comprising nanocrystals.

10. A method of making a semiconductor device on a semiconductor layer, comprising:

forming a gate dielectric over the semiconductor layer;

forming a layer of gate material over the gate dielectric;

etching the layer of gate material to form a select gate;

forming a storage layer that extends over the select gate and over a portion of the semiconductor layer;

depositing an amorphous silicon layer over the storage layer;

etching the amorphous silicon layer to form a control gate; and

annealing the semiconductor device to crystallize the amorphous silicon layer,

wherein the step of depositing the amorphous silicon layer is performed by sputtering.

11. A method of making a semiconductor device on a semiconductor layer, comprising:

forming a gate dielectric over the semiconductor layer;

forming a layer of gate material over the gate dielectric;

etching the layer of gate material to form a select gate;

forming a charge storage layer that extends over the select gate and over a portion of the semiconductor layer;

depositing an amorphous silicon layer over the charge storage layer;

etching the amorphous silicon layer to form a control gate;

forming a liner on the semiconductor device;

forming a capping layer over the liner; and

annealing the semiconductor device to crystallize the amorphous silicon layer.

12. The method of claim 11 , further comprising removing the capping layer from over the semiconductor device after the step of annealing the semiconductor device.

13. The method of claim 11 wherein forming the capping layer further comprises forming the capping layer from tensile stressed silicon nitride.

14. The method of claim 11 , wherein forming the capping layer further comprises depositing a silicon nitride layer having a thickness in a range of 20 to 200 nanometers.

15. The method of claim 11 , wherein annealing the semiconductor device to crystallize the amorphous silicon layer further comprises annealing the semiconductor device at a temperature in a range of 500 to 1100 degrees Celsius.

16. The method of claim 11 , wherein depositing the amorphous silicon layer over the charge storage layer is further characterized by sputtering silicon and an impurity.

17. The method of claim 11 , wherein forming the charge storage layer is further characterized by the charge storage layer comprising nanocrystals.

18. A method of making a semiconductor device on a semiconductor layer, comprising:

forming a gate dielectric over the semiconductor layer;

forming a polysilicon layer over the gate dielectric;

etching the polysilicon layer to form a select gate;

forming a charge storage layer that extends over the select gate and over a portion of the semiconductor layer, wherein the charge storage layer comprises nanocrystals;

depositing an amorphous silicon layer over the charge storage layer;

etching the amorphous silicon layer to form a control gate, the control gate having a portion formed over a portion of the select gate;

forming an insulating liner on the semiconductor device;

forming a tensile stressed silicon nitride layer over the insulating liner;

annealing the semiconductor device to crystallize the amorphous silicon layer; and

removing the tensile stressed silicon nitride layer.

19. The method of claim 18 , wherein:

forming the tensile stressed silicon nitride layer further comprises depositing a silicon nitride layer having a thickness in a range of 20 to 200 nanometers;

annealing the semiconductor device to crystallize the amorphous silicon layer further comprises annealing the semiconductor device at a temperature in a range of 500 to 1100 degrees Celsius; and

depositing the amorphous silicon layer over the charge storage layer is by sputtering.

Assignments (18)