IP Library › Granted Patent US 8,640,084
Granted Patent B2
US 8,640,084 · App. 12/415,963 · Granted Jan 28, 2014

Generating validation test suites

Inventor: Praveen K. Murthy (Fremont, CA)
Assignee: Fujitsu Limited
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Quick Facts
Patent No.
US 8,640,084
App. No.
12/415,963
Granted
Jan 28, 2014
Kind
B2
Abstract

In one embodiment, a method includes accessing a modeling language representation of a system under test. The representation includes one or more Message Sequence Charts (MSCs). One or more of the MSCs includes one or more conditional constructs including at least one or more guards or one or more loops. The method includes generating one or more use scenarios based on the modeling language representation and generating one or more validation test suites based on the one or more use scenarios.

Claims (32)

1. A method comprising:

using one or more computer systems, accessing a modeling language representation of a system under test, the representation comprising one or more Message Sequence Charts (MSCs), one or more of the MSCs comprising one or more conditional constructs including at least one or more guards or one or more loops;

using the computer systems, generating one or more use scenarios based on the modeling language representation, wherein generating the one or more use scenarios comprises identifying and generating one or more use scenarios for each combination of two MSCs in the order indicated in a directed graph;

and using the computer systems, generating one or more validation test suites based on the one or more use scenarios.

2. The method of claim 1 , wherein one or more of the one or more conditional constructs comprise one or more transitions selected from the group consisting of one or more Alternatives, Options, Breaks, Parallels, Critical Regions, or Loops specified in Unified Modeling Language (UML).

3. The method of claim 1 , wherein one or more of the MSCs are hierarchically arranged MSCs.

4. The method of claim 1 , wherein one or more of the MSCs are deterministic.

5. The method of claim 1 , wherein one or more of the MSCs are non-deterministic.

6. The method of claim 1 , wherein generating one or more use scenarios comprises identifying and generating one or more use scenarios for every MSC in a directed graph.

7. The method of claim 6 , wherein generating one or more use scenarios for every MSC in a directed graph comprises using a postman algorithm to generate a postman tour of the directed graph.

8. The method of claim 6 , wherein generating one or more use scenarios for every MSC in the directed graph comprises identifying and generating use scenarios for every possible complete path through the directed graph.

9. The method of claim 1 , wherein generating one or more use scenarios comprises generating one or more use scenarios that test every transition between the MSCs.

10. The method of claim 9 , wherein one or more of the validation test suites are operable to keep track of which transitions are actually visited during execution of the validation test suite.

11. The method of claim 1 , wherein one or more of the validation test suites are operable to act as a state machine to interact with the system under test according to one or more of the use scenarios.

12. The method of claim 1 , wherein the system under test comprises hardware, software, or a combination of hardware and software.

13. The method of claim 1 , wherein the system under test comprises a finite state machine (FSM).

14. One or more non-transitory computer-readable tangible storage media, encoding software that is operable when executed to:

access a modeling language representation of a system under test, the representation comprising one or more Message Sequence Charts (MSCs), one or more of the MSCs comprising one or more conditional constructs including at least one or more guards or one or more loops;

generate one or more use scenarios based on the modeling language representation, wherein generating the one or more use scenarios comprises identifying and generating one or more use scenarios for each combination of two MSCs in the order indicated in a directed graph;

and generate one or more validation test suites based on the one or more use scenarios.

15. The media of claim 14 , wherein one or more of the one or more conditional constructs comprise one or more transitions selected from the group consisting of one or more Alternatives, Options, Breaks, Parallels, Critical Regions, or Loops specified in Unified Modeling Language (UML).

16. The media of claim 14 , wherein one or more of the MSCs are hierarchically arranged MSCs.

17. The media of claim 14 , wherein one or more of the MSCs are deterministic.

18. The media of claim 14 , wherein one or more of the MSCs are non-deterministic.

19. The media of claim 14 , wherein the software being operable to generate one or more use scenarios comprises the software being operable to identify and generate one or more use scenarios for every MSC in a directed graph.

20. The media of claim 19 , wherein the software being operable to generate one or more use scenarios for every MSC in a directed graph comprises the software being operable to use a postman algorithm to generate a postman tour of the directed graph.

21. The media of claim 19 , wherein the software being operable to generate one or more use scenarios for every MSC in the directed graph comprises the software being operable to identify and generate use scenarios for every possible complete path through the directed graph.

22. The media of claim 14 , wherein the software being operable to generate one or more use scenarios comprises the software being operable to generate one or more use scenarios that test every transition between the MSCs.

23. The media of claim 22 , wherein the software being operable to generate one or more use scenarios that test every transition between the MSCs comprises the software being operable to keep track of which transitions are actually visited during execution of the software.

24. The media of claim 14 , wherein one or more of the validation test suites are operable to act as a state machine to interact with the system under test according to one or more of the use scenarios.

25. The media of claim 14 , wherein the system under test comprises hardware, software, or a combination of hardware and software.

26. The media of claim 14 , wherein the system under test comprises a finite state machine (FSM).

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 31, 2009
From: MURTHY, PRAVEEN K.
To: FUJITSU LIMITED
Reel/Frame 022479/0696 →
Continuity (1)
Related Publication 20100251209A1 · Sep 30, 2010