Narrow width metal oxide semiconductor transistor
View Patent ↗Disclosed is a semiconductor transistor for enhancing performance of PMOS and NMOS transistors, particularly current driving performance, while reducing a narrow width effect. A narrow width MOS transistor includes: a channel of which width is W 0 and length is L 0 ; an active area including source and drain areas formed at both sides with the channel as a center; a gate insulating layer formed on the channel; a gate conductor formed on the gate insulating layer and intersecting the active area; a first additional active area of width is larger than that W 0 of the channel as an active area added to the source area; and a second additional active area of width is larger than that W 0 of the channel as an active area added to the drain area. When the structure of the transistor having the additional active areas is applied to NMOS and PMOS transistors, a driving current is represented as 107.27% and 103.31%, respectively. Accordingly, the driving currents of both PMOS and NMOS transistors are enhanced.
1. A method of making a MOS transistor, comprising:
forming a gate insulating layer on a semiconductor substrate;
forming a gate conductor on the gate insulating layer over a channel in the substrate, the channel having a width W 0 and a length L 0 , and the gate conductor having a contact region not intersecting an active area of the MOS transistor; and
implanting dopant ions using a photo mask in an active area of the substrate to form (i) a source and a drain on opposite sides of the channel, each of the source and the drain having a width equal to W 0 , a length L s/d , and a contact region, and (ii) at least one of an additional source area and an additional drain area, the additional source area and/or additional drain area extending between the contact region of the source and/or the drain to the contact region of the gate conductor, and having a width W 1 larger than W 0 and a length L 1 less than L s/d .
2. The method of claim 1 , comprising forming both the additional source area and the additional drain area.
3. The method of claim 2 , wherein the source, the drain, the additional source area and the additional drain area are formed simultaneously.
4. The method of claim 1 , wherein forming the gate conductor further comprises forming the contact region on the gate conductor, the contact region having a length and a width that are both greater than a length of the gate conductor.
5. The method of claim 4 , wherein the gate conductor has a first portion intersecting the channel and a second portion connected to the contact region.
6. The method of claim 5 , wherein the additional source area and/or the additional drain area are adjacent to a third portion of the gate conductor.
7. The method of claim 6 , wherein the gate conductor comprises a fourth portion connected at one end to the second portion of the gate conductor and at another end to the third portion of the gate conductor.
8. The method of claim 7 , wherein the fourth portion of the gate conductor is perpendicular to the first and the third portions, and is not in the active area.
9. The method of claim 6 , wherein the third portion of the gate conductor does not intersect the additional source area and/or the additional drain area.
10. The method of claim 1 , wherein implanting dopant ions in the active area comprises implanting N-type impurities.
11. The method of claim 1 , wherein implanting dopant ions in the active area comprises implanting P-type impurities.
12. The method of claim 1 , wherein the additional source area is continuous with the source.
13. The method of claim 1 , wherein the additional drain area is continuous with the drain.
14. The method of claim 4 , further comprising forming one or more contacts on the contact region.
15. The method of claim 1 , further comprising forming the contact regions in the source and the drain.
16. The method of claim 15 , further comprising forming one or more contacts on each of the source and the drain.
17. The method of claim 12 , wherein the length L 1 of the additional source area is sufficiently smaller than the length L s/d of the source so that the width W 0 of the channel does not increase due to the additional source area.
18. The method of claim 13 , wherein the length of the additional drain area is sufficiently smaller than the length L s/d of the drain so that the width W 0 of the channel does not increase due to the additional drain source area.