SEMICONDUCTOR INTEGRATED CIRCUIT AND LAYOUT METHOD FOR THE SAME

1 . A semiconductor integrated circuit comprising:

a first via-contact configured to connect a first interconnection pattern provided for a first interconnection layer and a second interconnection pattern provided for a second interconnection layer;

a second via-contact configured to connect a third interconnection pattern provided for said first interconnection layer and said second interconnection pattern; and

a redundant interconnection pattern formed in said first interconnection layer and configured to connect said first interconnection pattern and said third interconnection pattern to overlap above said second interconnection pattern.

2 . The semiconductor integrated circuit according to claim 1 , wherein said redundant interconnection pattern is provided between said first via-contact and said second via-contact to extend in a direction said second interconnection pattern.

3 . The semiconductor integrated circuit according to claim 1 , further comprising:

a third via-contact configured to connect said redundant interconnection pattern and said second interconnection pattern,

wherein said third via-contact is arranged between said first via-contact and said second via-contact.

4 . The semiconductor integrated circuit according to claim 1 , wherein said first interconnection layer is an n th interconnection layer (n is an optional natural number), and

said second interconnection layer is an (n+1) th or (n−1) th interconnection layer.

5 . A layout method of a semiconductor integrated circuit, comprising:

determining an interconnection layout of a semiconductor integrated circuit based on a netlist, a cell library and a connection rule;

specifying a first interconnection layer, a second interconnection layer, a first via-contact and a second via-contact, wherein an interlayer insulating film is provided between said first interconnection layer and said second interconnection layer, and said first and second via-contacts are formed in said interlayer insulating film, and applied with a same voltage;

checking whether or not a line between said first and second via-contacts extends along one of an X-axis and a Y-axis;

checking a first interconnection pattern in said first interconnection layer of whether or not said first interconnection pattern is provided to connect said first and second via-contacts at their first ends, when the line extends along one of the X-axis and the Y-axis;

checking whether or not said first interconnection pattern is a linear pattern;

providing a redundant interconnection pattern to connect said first and second via-contacts at their second ends opposite to the first ends, when said first interconnection pattern is a linear pattern; and

performing a design rule check on an interconnection layout with said redundant interconnection pattern added.

6 . The layout method according to claim 5 , further comprising:

connecting the first end of said first via-contact and the first end of said second via-contact straight by said redundant interconnection pattern on a straight line, when said first interconnection pattern connected with the first end of said first via-contact is not connected with the first end of said second via-contact; and

connecting the second end of said first via-contact and the second end of said second via-contact by said redundant interconnection pattern on a straight line.

7 . The layout method according to claim 5 , further comprising:

arranging a third via-contact between said first via-contact and said second via-contact.

8 . A computer-readable recording medium in which a computer-readable program code is stored to realize a layout method of a semiconductor integrated circuit, wherein said layout method comprises:

determining an interconnection layout of a semiconductor integrated circuit based on a netlist, a cell library and a connection rule;

specifying a first interconnection layer, a second interconnection layer, a first via-contact and a second via-contact, wherein an interlayer insulating film is provided between said first interconnection layer and said second interconnection layer, and said first and second via-contacts are formed in said interlayer insulating film, and applied with a same voltage;

checking whether or not a line between said first and second via-contacts extends along one of an X-axis and a Y-axis;

checking a first interconnection pattern in said first interconnection layer of whether or not said first interconnection pattern is provided to connect said first and second via-contacts at their first ends, when the line extends along one of the X-axis and the Y-axis;

checking whether or not said first interconnection pattern is a linear pattern;

providing a redundant interconnection pattern to connect said first and second via-contacts at their second ends opposite to the first ends, when said first interconnection pattern is a linear pattern; and

performing g a design rule check on an interconnection layout with said redundant interconnection pattern added.

9 . The computer-readable recording medium according to claim 8 , wherein said layout method further comprises:

connecting the first end of said first via-contact and the first end of said second via-contact straight by said redundant interconnection pattern on a straight line, when said first interconnection pattern connected with the first end of said first via-contact is not connected with the first end of said second via-contact; and

connecting the second end of said first via-contact and the second end of said second via-contact by said redundant interconnection pattern on a straight line.

10 . The computer-readable recording medium according to claim 8 , wherein said layout method further comprises:

arranging a third via-contact between said first via-contact and said second via-contact.