Processor including age tracking of issue queue instructions
An information handling system includes a processor with an instruction issue queue (IQ) that may perform age tracking operations. The issue queue IQ maintains or stores instructions that may issue out-of-order in an internal data store IDS. The IDS organizes instructions in a queue position (QPOS) addressing arrangement. An age matrix of the IQ maintains a record of relative instruction aging for those instructions within the IDS. The age matrix updates latches or other memory cell data to reflect the changes in IDS instruction ages during a dispatch operation into the IQ. During dispatch of one or more instructions, the age matrix may update only those latches that require data change to reflect changing IDS instruction ages. The age matrix employs row and column data and clock controls to individually update those latches requiring update. The issue queue may selectively clock a row and a column of cells of the age matrix that correspond to a dispatched instruction's queue position while leaving other cells unclocked to conserve power.
1. A processor, comprising;
an issue queue to receive a set of dispatched instructions, the issue queue including:
an instruction data store (IDS) having a plurality of queue positions that store the set of dispatched instructions; and
an age matrix for managing a relative age of each dispatched instruction in the set of dispatched instructions stored in the IDS with respect to other dispatched instructions in the set of dispatched instructions stored in the IDS, wherein:
the age matrix includes a plurality of memory cells configured in a number of rows and a number of columns, and
during the dispatching of at least one dispatched instruction in the set of dispatched instructions, the issue queue:
stores the at least one dispatched instruction in the IDS,
updates the age matrix to reflect the age of the at least one instruction relative to other dispatched instructions in the IDS,
modifies the age matrix row memory cells to a first state and column memory cells to a second state corresponding to the at least one dispatched instruction's queue position to reflect the relative age of the at least one dispatched instruction with respect to other dispatched instructions in the IDS, and
for each row in the matrix, modifies a relative age storage element with an age value corresponding to a sum of the memory elements having the second state, wherein the age value indicates the age of each dispatched instruction in the set of dispatched instructions in the IDS.
2. The processor of claim 1 , further comprising a row and column logic controller, coupled to the memory cells of the age matrix, that selectively clocks a row and a column of the age matrix that correspond to the at least one dispatched instruction's queue position.
3. the processor of claim 2 , wherein the number of rows of memory cells in the age matrix equals the number of queue positions in the IDS, the number of columns of memory cells in the age matrix also being equal to the number of queue positions in the IDS.
4. The processor of claim 1 , wherein the at least one dispatched instruction includes first and second dispatched instructions dispatched at a same time such that, during dispatching of the first and second dispatched instructions, the IDS stores the first and second dispatched instructions in respective queue positions, and the issue queue modifies the age matrix to reflect the age of the first and second dispatched instructions relative to other dispatched instructions in the IDS.
5. The processor of claim 4 , wherein the age matrix exhibits an intersection of rows and columns of memory cells corresponding to the first and second dispatched instructions of the IDS, and wherein the intersection comprises four memory cells in a two-by-two matrix.
6. The processor of claim 5 , wherein the issue queue updates the rows of memory cells of the age matrix that correspond to the first and second dispatched instructions except for those memory cells in the intersection, with data to reflect the relative age of the first and second dispatched instructions with respect to other dispatched instructions in the IDS.
7. The processor of claim 6 , wherein the issue queue updates the columns of memory cells of the age matrix that correspond to the first and second dispatched instructions except for those memory cells in the intersection, with data to reflect the relative age of the first and second dispatched instructions with respect to other dispatched instructions in the IDS.
8. An information handling system (IHS), comprising:
a memory that stores an instruction stream that includes a plurality of instructions:
a processor, coupled to the memory, the processor including:
an issue queue to receive a set of dispatched instructions, the issue queue including:
an instruction data store (IDS) having a plurality of queue positions that store the set of dispatched instructions; and
an age matrix for managing a relative age of each dispatched instruction in the set of dispatched instructions stored in the IDS with respect to other dispatched instructions in the set of dispatched instructions stored in the IDS, wherein:
the age matrix includes a plurality of memory cells configured in a number of rows and a number of columns, and
during the dispatching of at least one dispatched instruction in the set of dispatched instructions, the issue queue:
stores the at least one dispatched instruction in the IDS,
updates the age matrix to reflect the age of the at least one instruction relative to other dispatched instructions in the IDS,
modifies the age matrix row memory cells to a first state and column memory cells to a second state corresponding to the at least one dispatched instruction's queue position to reflect the relative age of the at least one dispatched instruction with respect to other dispatched instructions in the IDS, and
for each row in the age matrix, modifies a relative age storage element with an age value corresponding to a sum of the memory elements having the second state, wherein the age value indicates the age of each dispatched instruction in the set of dispatched instructions in the IDS.
9. The IHS of claim 8 , further comprising a row and column logic controller, coupled to the memory cells of the age matrix, that selectively clocks a row and a column of the age matrix that correspond to the at least one dispatched instruction's queue position.
10. The IHS of claim 9 , wherein the number of rows of memory cells in the age matrix equals the number of queue positions in the IDS, the number of columns of memory cells in the age matrix also being equal to the number of queue positions in the IDS.
11. The IHS of claim 8 , wherein the at least one dispatched instruction includes first and second dispatched instructions such that, during dispatching of the first and second dispatched instructions, the IDS stores the first and second dispatched instructions in respective queue positions, and the issue queue modifies the age matrix to reflect the age of the first and second dispatched instructions relative to other dispatched instructions in the IDS.
12. The IHS of claim 11 , wherein the age matrix exhibits an intersection of rows and columns of memory cells corresponding to the first and second dispatched instructions of the IDS, and wherein the intersection comprises four memory cells in a two-by-two matrix.
13. The IHS of claim 12 , wherein the issue queue updates the rows of memory cells of the age matrix that correspond to the first and second dispatched instructions except for those memory cells in the intersection, with data to reflect the relative age of the first and second dispatched instructions with respect to other dispatched instructions in the IDS.
14. The IHS of claim 13 , wherein the issue queue updates the columns of memory cells of the age matrix that correspond to the first and second dispatched instructions except for those memory cells in the intersection, with data to reflect the relative age of the first and second dispatched instructions with respect to other dispatched instructions in the IDS.