Formation of through-wafer electrical interconnections and other structures using a thin dielectric membrane
View Patent ↗Providing through-wafer interconnections in a semiconductor wafer includes forming a sacrificial membrane in a pre-existing semiconductor wafer, depositing metallization over one side of the wafer so as to cover exposed portions of the sacrificial membrane facing the one side of the wafer, removing exposed portions of the sacrificial membrane facing the other side of the wafer, and depositing metallization over the other side of the wafer so as to contact the previously deposited metallization. Techniques also are disclosed for providing capacitive and other structures using thin metal membranes.
1. A method of providing through-wafer interconnections in a semiconductor wafer having first and second sides, the method comprising:
etching the first side of the wafer to form a cavity;
providing an etch stop layer over the first side of the wafer, wherein the etch stop layer covers surfaces in the cavity;
etching the second side of the wafer to form one or more micro-vias such that the one or more micro-vias reach the etch stop layer;
depositing metallization over one of the first and second sides of the wafer;
subsequently removing regions of the etch stop layer from areas corresponding to where the one or more micro-vias were formed; and
depositing metallization over the other one of the first and second sides of the wafer so that the metallization deposited over the first side is in contact with the metallization deposited over the second side to form the through-wafer interconnections in areas corresponding to where the one or more micro-vias were formed.
2. The method of claim 1 wherein the semiconductor wafer comprises silicon, and the etch stop layer comprises at least one of silicon dioxide or silicon nitride.
3. The method of claim 1 wherein the semiconductor wafer comprises silicon, and wherein providing an etch stop layer includes thermally growing a silicon dioxide layer.
4. The method of claim 1 wherein a dimension of the cavity is larger than a corresponding dimension of each of the one or more micro-vias.
5. The method of claim 1 wherein the second side of the wafer is etched such that the one or more micro-vias reach a depth so as to expose thin membranes of the etch stop layer in the cavity.
6. The method of claim 1 including providing an isolation layer over surfaces of the semiconductor wafer prior to depositing metallization over the one side of the wafer.
7. The method of claim 1 including:
selectively providing an oxide layer over the first and second sides of the wafer after forming the one or more micro-vias in the second side, such that portions of the etch stop layer remain exposed in the cavity, and wherein the thickness of the oxide layer is greater than the thickness of the etch stop layer; and
wherein removing regions of the etch stop layer includes using an etchant that etches both the etch stop layer and the oxide layer.
8. The method of claim 7 including thermally growing the oxide layer.
9. The method of claim 7 wherein the oxide layer is at least three times as thick as the etch stop layer.
10. The method of claim 1 wherein the semiconductor wafer comprises silicon and wherein a dimension of the cavity is larger than a corresponding dimension of each of the one or more micro-vias,
wherein the second side of the wafer is etched such that the one or more micro-vias reach a depth so as to expose thin membranes of the etch stop layer in the cavity, and
wherein the method further includes selectively providing an oxide layer over the first and second sides of the wafer after forming the one or more micro-vias in the second side, such that portions of the etch stop layer remain exposed in the cavity and such that the thickness of the oxide layer is greater than the thickness of the etch stop layer.
11. The method of claim 10 including thermally growing the oxide layer.