SEMICONDUCTOR MEMORY DEVICE AND SYSTEM USING SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device comprises a RAM (Random Access Memory), an ODT (On-Die Termination) circuits and a JTAG (Joint Test Action Group) circuit. The RAM is connected to a data input-output port. The ODT circuit is provided between the data input-output port and a termination port. The JTAG circuit controls the ODT circuit in response to an instruction such that the data input-output port and the termination port are electrically connected with each other.
1 . A semiconductor memory device comprising:
a random access memory connected to a data input-output port;
an on-die termination circuit provided between said data input-output port and a termination port; and
a joint test action group circuit configured to control said on-die termination circuit in response to an instruction such that said data input-output port and said termination port are electrically connected with each other.
2 . The semiconductor memory device according to claim 1 ,
wherein said random access memory is a static random access memory.
3 . The semiconductor memory device according to claim 2 ,
wherein said static random access memory comprises:
a memory core; and
a data input-output unit connected between said memory core and said data input-output port and configured to transfer data between said memory core and said data input-output port.
4 . The semiconductor memory device according to claim 1 ,
wherein said on-die termination circuit comprises:
a termination resistance whose one end is connected to said random access memory and said data input-output port; and
a switch provided between the other end of said termination resistance and said termination port and configured to be turned on in response to an enable signal such that said data input-output port and said termination port are electrically connected with each other through said termination resistance,
wherein said joint test action group circuit outputs said enable signal in response to said instruction.
5 . The semiconductor memory device according to claim 1 ,
wherein said instruction is not issued during a test logic reset of said joint test action group circuit.
6 . A system comprising:
a semiconductor memory device; and
an instruction issuing unit configured to issue an instruction and output said instruction to said semiconductor memory device,
wherein said semiconductor memory device comprises:
a random access memory connected to a data input-output port;
an on-die termination circuit provided between said data input-output port and a termination port; and
a joint test action group circuit configured to control said on-die termination circuit in response to said instruction such that said data input-output port and said termination port are electrically connected with each other.
7 . The system according to claim 6 ,
wherein said random access memory is a static random access memory.
8 . The system according to claim 6 ,
wherein said on-die termination circuit comprises:
a termination resistance whose one end is connected to said random access memory and said data input-output port; and
a switch provided between the other end of said termination resistance and said termination port and configured to be turned on in response to an enable signal such that said data input-output port and said termination port are electrically connected with each other through said termination resistance,
wherein said joint test action group circuit outputs said enable signal in response to said instruction.
9 . The system according to claim 6 ,
wherein said instruction issuing unit does not issue said instruction during a test logic reset of said joint test action group circuit.
10 . The system according to claim 6 ,
wherein said instruction issuing unit is software-based.