Chemical mechanical polishing (CMP) method for gate last process

1. A method for fabricating a semiconductor device, the method comprising:

providing a semiconductor substrate;

forming a plurality of transistors in the semiconductor substrate, each transistor having a dummy gate structure;

forming a contact etch stop layer (CESL) over the substrate including the dummy gate structures;

forming a first dielectric layer to fill a portion of each region between adjacent dummy gate structures;

forming a chemical mechanical polishing (CMP) stop layer over the CESL and first dielectric layer;

forming a second dielectric layer over the CMP stop layer;

performing a CMP on the second dielectric layer that substantially stops at the CMP stop layer; and

performing an overpolishing to expose the dummy gate structures.

2. The method of claim 1 , wherein the CMP stop layer includes silicon nitride.

3. The method of claim 1 , wherein the CESL layer includes silicon nitride.

4. The method of claim 1 , further comprising removing the dummy gate structures and replacing each of them with a metal gate.

5. The method of claim 4 , wherein the removing the dummy gate structures and replacing each of them with a metal gate includes:

performing an etch back process to remove each of the dummy gate structures thereby forming a trench;

filling a portion of the trench with a work function metal layer;

filling a remaining portion of the trench with a filler metal layer; and

performing another CMP to remove the filler metal layer and the work function layer outside of the trench.

6. The method of claim 1 , wherein the first dielectric layer includes an oxide formed by a high-aspect ratio process (HARP).

7. The method of claim 6 , wherein the second dielectric layer includes an oxide formed by a high plasma density (HDP) deposition process.

8. The method of claim 1 , wherein the overpolishing is a continuation of the CMP.

9. A method for fabricating a semiconductor device, the method comprising:

forming a plurality dummy gate structures over a semiconductor substrate;

forming a first stop layer over the semiconductor substrate including the plurality of dummy gate structures, the first stop layer being formed of a first material;

forming a first oxide layer to fill a portion of a gap between adjacent dummy gate structures;

forming a second stop layer over the first stop layer and first dielectric layer, the second stop layer being formed of a second material;

forming a second oxide layer over the second stop layer filling a remainder of the gap;

performing a chemical mechanical polishing (CMP) on the second oxide layer that substantially stops at the second stop layer;

performing an overpolishing to remove portions of the second stop layer and the first stop layer thereby exposing the dummy gate structures; and

removing the dummy gate structures and replacing them with metal gates.

10. The method of claim 9 , wherein the first material and the second material are formed of the same material.

11. The method of claim 10 , wherein the first material and the second material are formed of silicon nitride.

12. The method of claim 9 , wherein the first stop layer includes a contact etch stop layer (CESL).

13. The method of claim 12 , wherein the second stop layer includes a CMP stop layer.

14. The method of claim 9 , wherein the dummy gate structures include dummy polysilicon gates.

15. A method of fabricating a semiconductor device, comprising:

providing a substrate having a plurality of gate structures formed thereon, the gates being separated from one another by a plurality of respective gap regions;

forming an etch-stop layer over the substrate and the plurality of gates;

partially filling the plurality of gap regions with a plurality of gap-filling components;

forming a polishing-stop layer over the etch-stop layer and the gap-filling components;

forming a material layer over the polishing-stop layer, the material layer filling remainder portions of the gap regions;

performing a first polishing process on the semiconductor device until the polishing-stop layer is exposed; and

performing a second polishing process on the semiconductor device until the gate structures are exposed.

16. The method of claim 15 , wherein the first and second polishing processes are two stages of a chemical mechanical polishing process.

17. The method of claim 15 , wherein the gate structures are dummy gate structures;

and further including: replacing the dummy gate structures with metal gate structures.

18. The method of claim 15 , wherein the partially filling the plurality of gap regions is carried out using a high-aspect ratio deposition process followed by an etch-back process.

19. The method of claim 15 , wherein the forming the material layer is carried out using a high density plasma deposition process.

20. The method of claim 15 , wherein:

the forming the etching-stop layer is carried out in a manner so that the etching-stop layer has a thickness that is in a range from about 150 Angstroms to about 500 Angstroms; and

the forming the polishing-stop layer is carried out in a manner so that the polishing-stop layer has a thickness that is in a range from about 40 Angstroms to about 80 Angstroms.