Patent Assignment
Reel/Frame 068326/0474
Assignment of Assignor's Interest
Recorded: 2024-08-05
Pages: 15
Assignor
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
Executed: 2024-07-19
Assignee
PARABELLUM STRATEGIC OPPORTUNITIES FUND LLC
251 LITTLE FALLS DRIVE, WILMINGTON, DELAWARE, 19808-1674
Covered Properties
(197)
Methods for Fabricating Image Sensor Devices
Structures for Preventing Cross-Talk Between Through-Silicon Vias and Integrated Circuits
Chemical Mechanical Polishing (Cmp) Method for Gate Last Process
Novel High-K Metal Gate Cmos Patterning Method
Copper Bump Joint Structures with Improved Crack Resistance
Integrated Semiconductor Structure for Sram and Fabrication Methods Thereof
Methods for Fabricating Image Sensor Devices
Novel Structures and Methods to Stop Contact Metal from Extruding into Replacement Gates
Integrated Circuit Including Finfets and Methods for Forming the Same
Protection Layer for Adhesive Material at Wafer Edge
Package Systems Having Interposers with Interconnection Structures
Embedded 3D Interposer Structure
Controlling the Shape of Source/Drain Regions in Finfets
Fin-Like Field Effect Transistor (Finfet) Device and Method of Manufacturing Same
Robust Joint Structure for Flip-Chip Bonding
Conductive Pillar Structure
Fin-Like Field Effect Transistor (Finfet) Device and Method of Manufacturing Same
Molded Chip Interposer Structure and Methods
Distributed Metal Routing
End-To-End Gap Fill Using Dielectric Film
Preventing the Cracking of Passivation Layers on Ultra-Thick Metals
Adaptive Fin Design for Finfets
Semiconductor Device Having a Bonding Pad and Shield Structure of Different Thickness
Chemical Mechanical Polishing (Cmp) Method for Gate Last Process
Integrated Circuits
Selective Fin-Shaping Process Using Plasma Doping and Etching for 3-Dimensional Transistor Applications
Structures for Preventing Cross-talk Between Through-Silicon Vias and Integrated Circuits
Bump Structural Designs to Minimize Package Defects
Methods and Apparatus for Sram Cell Structure
Metal Gate Finfet Device and Method of Fabricating Thereof
Strained Structure of Semiconductor Device and Method of Making the Strained Structure
Elongated Bumps in Integrated Circuit Devices
Protection Layer for Adhesive Material at Wafer Edge
Semiconductor Integrated Circuit with Metal Gate
Patent:
8,507,979 →
Application:
13/563,470 →
Controlling the Shape of Source/Drain Regions in FinFETs
Integrated Semiconductor Structure for Sram and Fabrication Methods Thereof
Molded Chip Interposer Structure and Methods
FinFET with Embedded MOS Varactor and Method of Making Same
Semiconductor Device Having Modified Profile Metal Gate
Fin-Like Field Effect Transistor (FinFET) Device and Method of Manufacturing Same
Back Side Illumination (Bsi) Sensors, Manufacturing Methods Thereof, and Semiconductor Device Manufacturing Methods
Bump Structures for Semiconductor Package
End-To-End Gap Fill Using Dielectric Film
Protection Layer for Adhesive Material at Wafer Edge
Embedded 3D Interposer Structure
Methods to Stop Contact Metal from Extruding into Replacement Gates
Interconnect Structure and Method for Forming the Same
Mechanisms for Forming Image Sensor Device
Semiconductor Device and Formation Thereof
Semiconductor Structure and Manufacturing Method Thereof
Packages with Through-Vias Having Tapered Ends
Bump Structure and Method for Forming the Same
Bump Structural Designs to Minimize Package Defects
Semiconductor Device Having a Bonding Pad and Shield Structure and Method of Manufacturing the Same
Adaptive Fin Design for FinFETs
Semiconductor Package and Method
Method of Manufacturing a Fin-Like Field Effect Transistor (Finfet) Device
Multi-Gate Device Structure Including a Fin-Embedded Isolation Region and Methods Thereof
Method of Forming Package Systems Having Interposers
Integrated Circuits and Methods of Forming Integrated Circuits
Metal Gate Finfet Device
Selective Fin-Shaping Process
Controlling the Shape of Source/Drain Regions in FinFETs
Interconnect Structure and Method for Forming the Same
Source/Drain Regions for Fin Field Effect Transistors and Methods of Forming Same
Methods and Apparatus for SRAM Cell Structure
Finfet with Embedded Mos Varactor and Method of Making Same
Distributed Metal Routing
Structure and Formation Method of Semiconductor Device Structure
Semiconductor Structure and Manufacturing Method Thereof
Method and Structure for Semiconductor Device Having Gate Spacer Protection Layer
Self-Aligned Back Side Deep Trench Isolation Structure
Semiconductor Device and Manufacturing Method Thereof
Method of Making a Strained Structure of a Semiconductor Device
Bump Structural Designs to Minimize Package Defects
Method for Forming Package Systems Having Interposers
Methods of Forming Multi-Die Package Structures Including Redistribution Layers
Image Sensor with Wide Contact
Fin-Like Field Effect Transistor (Finfet) Device and Method of Manufacturing Same
Structure and Formation Method for Chip Package
Semiconductor Device Having Modified Profile Metal Gate
Lid Structure for a Semiconductor Device Package and Method for Forming the Same
Semiconductor Device and Manufacturing Method Thereof
Semiconductor Device and Formation Thereof
Methods and Apparatus for SRAM Cell Structure
Integrated Circuits and Methods of Forming Integrated Circuits
Chip Package with Thermal Dissipation Structure and Method for Forming the Same
Multi-Gate Device Structure Including a Fin-Embedded Isolation Region and Methods Thereof
Source/Drain Regions for Fin Field Effect Transistors and Methods of Forming Same
Structure and Formation Method of Semiconductor Device with Metal Gate
Method of Manufacturing a Semiconductor Device with Separated Merged Source/Drain Structure
Method for Manufacturing Image Sensor Structure Having Wide Contact
Semiconductor Device
Method of Forming Absorption Enhancement Structure for Image Sensor
Thermal Interface Material Having Different Thicknesses In Packages
Method of Fabricating a Semiconductor Device Having Modified Profile Metal Gate
Structure and Formation Method for Chip Package
Self-Aligned Back Side Deep Trench Isolation Structure
Packages with Through-Vias Having Tapered Ends
Vias for Cobalt-Based Interconnects and Methods of Fabrication Thereof
Structure and Method for FinFET Device with Asymmetric Contact
Methods of Forming Multi-Die Package Structures Including Redistribution Layers
Semiconductor Structure and Manufacturing Method Thereof
Semiconductor Device and Method for Manufacturing the Same
Semiconductor Structure and Associated Fabricating Method
Semiconductor Packages and Methods of Forming the Same
Patent:
10,157,892 →
Application:
15/719,511 →
Packaging with Subsrtates Connected by Conductive Bumps
Method for Forming a Lid Structure for a Semiconductor Device Package
Method and Structure for Semiconductor Device Having Gate Spacer Protection Layer
Fin-Like Field Effect Transistor (FinFET) Device and Method of Manufacturing Same
Semiconductor Device Having a Liner Layer with a Configured Profile and Method of Fabricating Thereof
Package on Package Structure
Sram Structure
Patent:
10,411,022 →
Application:
16/008,302 →
Embedded 3D Interposer Structure
Structure of Semiconductor Device Structure Having Fins
Packages with Through-Vias Having Tapered Ends
Semiconductor Structure with Source/Drain Multi-Layer Structure and Method for Forming the Same
Structure and Method for Finfet Device with Asymmetric Contact
Thermal Interface Material Having Different Thicknesses in Packages
Method of Manufacturing a Semiconductor Device with Separated Merged Source/Drain Structure
Method and Structure for Semiconductor Device Having Gate Spacer Protection Layer
Method for Forming Bump Structure
Method for Manufacturing Semiconductor Device
Integrated Circuit Package and Method
Patent:
10,504,824 →
Application:
16/138,099 →
Chip Package and Method of Forming the Same
Absorption Enhancement Structure for Image Sensor
Semiconductor Device Including a Liner Layer Between a Channel and a Source/Drain Epitaxial Layer
Absorption Enhancement Structure for Image Sensor
Gate-All-Around Structure and Methods of Forming the Same
Sram Structure and Method for Manufacturing Sram Structure
Structure and Method for Finfet Device with Asymmetric Contact
Semiconductor Device Having Modified Profile Metal Gate
Structure and Method for Semiconductor Devices
Embedded 3D Interposer Structure
Semiconductor Structure with Source/Drain Multi-Layer Structure and Method for Forming the Same
Semiconductor Structure and Associated Fabricating Method
Fin-Like Field Effect Transistor (FinFET) Device and Method of Manufacturing Same
Package on Package Structure
Absorption Enhancement Structure for Image Sensor
Semiconductor Device Having a Liner Layer with a Configured Profile
Integrated Circuit Package and Method
Vias for Cobalt-Based Interconnects and Methods of Fabrication Thereof
Memory Device and Method of Fabricating the Memory Device
Semiconductor Structure and Method for Forming the Same
Packages with Through-Vias Having Tapered Ends
Method for Manufacturing Semiconductor Device
Structure of Semiconductor Device Structure Having Fins
Method of Fabricating a Semiconductor Device Having a Liner Layer with a Configured Profile
Semiconductor Device
Manufacturing Method of a Semiconductor Device
Structure and Method for FinFET Device with Asymmetric Contact
Absorption Enhancement Structure for Image Sensor
Thermal Interface Material Having Different Thicknesses in Packages
Semiconductor Device Structure and Method for Forming the Same
Multi-Die Package Structures Including Redistribution Layers
Sram Structure and Method for Manufacturing Sram Structure
Semiconductor Structure and Associated Fabricating Method
Method and Structure for Semiconductor Device Having Gate Spacer Protection Layer
Semiconductor Structure with Source/Drain Multi-Layer Structure and Method for Forming the Same
Gate-All-Around Structure and Methods of Forming the Same
Semiconductor Device and Method for Forming the Same
Integrated Circuit Package and Method
Semiconductor Device Having Modified Profile Metal Gate
Gate All-Around Semiconductor Device
Memory Device and Method of Fabricating the Memory Device
Structure and Method for Semiconductor Devices
Contact Structure of a Semiconductor Device
Package on Package Structure
Chip Package and Method of Forming the Same
Semiconductor Structure and Method for Forming the Same
Vias for Cobalt-Based Interconnects and Methods of Fabrication Thereof
Structure and Method for FinFET Device with Asymmetric Contact
Semiconductor Device Structure with Source/Drain Structure
Method and Structure for Semiconductor Device Having Gate Spacer Protection Layer
Semiconductor Device and Method for Forming the Same
Semiconductor Device
Integrated Circuit Package and Method
Semiconductor Structure with Source/Drain Multi-Layer Structure and Method for Forming the Same
Gate-All-Around Structure and Methods of Forming the Same
Semiconductor Device and Method for Forming the Same
Structure of Semiconductor Device Structure Having Fins
Chip Package and Method of Forming the Same
Semiconductor Structure and Associated Fabricating Method
Structure and Method for Semiconductor Devices
Thermal Interface Material Having Different Thicknesses in Packages
Application:
18/422,550 →
Publication:
US 2024/0162166
Vias for Cobalt-Based Interconnects and Methods of Fabrication Thereof
Contact Structure of a Semiconductor Device
Multi-Die Package Structures Including Redistribution Layers
Semiconductor Structure with Source/Drain Multi-Layer Structure and Method for Forming the Same
Structure and Method for FinFET Device with Asymmetric Contact
Package on Package Structure
Application:
18/659,033 →
Publication:
US 2024/0355795
Semiconductor Device
Manufacturing Method of a Semiconductor Device
Application:
18/676,539 →
Publication:
US 2024/0379382
Multi-Die Package Structures Including an Interconnected Package Component disposed in a Substrate Cavity
Gate-All-Around Structure and Methods of Forming the Same
Method and Structure for Semiconductor Device Having Gate Spacer Protection Layer
Application:
18/733,664 →
Publication:
US 2024/0412975
Semiconductor Device and Manufacturing Method Thereof
Application:
18/733,674 →
Publication:
US 2024/0395864
Related Assignments
(18)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Sep 13, 2006
From: SHIAU, GWO-YUH; LIU, MING-CHYI; HSIEH, YUAN-CHIH; FU, SHIH-CHI
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.
Reel/Frame 018237/0755 →
Assignment of Assignor's Interest
Nov 26, 2007
From: KUO, CHEN-CHENG
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 020153/0784 →
Assignment of Assignor's Interest
Apr 14, 2009
From: CHUANG, HARRY; THEI, KONG-BENG; LAI, SU-CHEN; SHEN, GARY
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 022544/0936 →
Assignment of Assignor's Interest
Dec 14, 2009
From: THEI, KONG-BENG; CHUANG, HARRY; CHEN, RYAN CHIA-JEN; LAI, SU-CHEN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 023646/0751 →
Assignment of Assignor's Interest
Jan 21, 2010
From: HSIAO, CHING-WEN; WU, JIUN YI; HUANG, RU-YING; CHEN, CHEN-SHIEN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 023826/0978 →
Assignment of Assignor's Interest
Feb 23, 2010
From: SHIAU, GWO-YUH; LIU, MING-CHYI; HSIEH, YUAN-CHIH; FU, SHIH-CHI
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 023974/0927 →
Assignment of Assignor's Interest
Feb 26, 2010
From: TEO, LEE-WEE; ZHU, MING; LEE, CHI-JU; CHUNG, SHENG-CHEN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 023996/0459 →
Assignment of Assignor's Interest
Mar 25, 2010
From: CHEN, HUNG-MING; YU, SHAO-MING; CHANG, CHANG-YUN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 024136/0522 →
Assignment of Assignor's Interest
Apr 29, 2010
From: CHIOU, WEN-CHIH; WU, WENG-JIN; SHUE, SHAU-LIN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 024307/0774 →
Assignment of Assignor's Interest
May 13, 2010
From: HUNG, SHENG CHIANG; HUANG, HUAI-YING; WANG, PING-WEI
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 024383/0052 →
Assignment of Assignor's Interest
May 18, 2010
From: LIN, YUNG-CHI; LIN, JING-CHENG; YU, CHEN-HUA
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 024400/0204 →
Assignment of Assignor's Interest
Jun 30, 2010
From: SHIH, YING-CHING; LIN, JING-CHENG; CHIOU, WEN-CHIH; JENG, SHIN-PUU
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 024619/0856 →
Assignment of Assignor's Interest
Jul 7, 2010
From: KWOK, TSZ-MEI; SU, CHIEN-CHANG; CHEN, KUAN-YU; SUNG, HSUEH-CHANG
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 024647/0682 →
Assignment of Assignor's Interest
Jul 15, 2010
From: PERNG, TSU-HSIN; YEH, CHIH CHIEH; CHEN, TZU-CHIANG; HO, CHIA-CHENG
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 024692/0193 →
Assignment of Assignor's Interest
Jul 23, 2010
From: HSIAO, CHING-WEN; CHUANG, YAO-CHUN; CHEN, CHEN-SHIEN; KUO, CHEN-CHENG
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 024731/0367 →
Assignment of Assignor's Interest
Aug 10, 2010
From: TEO, LEE-WEE; ZHU, MING; LEE, CHI-JU; CHUNG, SHENG-CHEN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 024816/0543 →
Assignment of Assignor's Interest
Oct 18, 2010
From: CHANG, CHIH-HAO; XU, JEFF J.
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 025155/0073 →
Assignment of Assignor's Interest
Nov 5, 2010
From: LIN, CHIH-WEI; CHENG, MING-DA; LU, WEN-HSIUNG; CHOU, MENG-WEI
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 025324/0975 →