Semiconductor structure and associated fabricating method
View Patent ↗A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an isolation region adjacent to the drain region; a gate electrode over the substrate and further downwardly extends into the substrate, wherein a portion of the gate electrode below a top surface of the substrate abuts the isolation region; and a source region and a drain region formed in the substrate on either side of the gate structure. An associated method for fabricating the semiconductor structure is also disclosed.
1. A method for fabricating a semiconductor structure, comprising:
providing a substrate;
forming an isolation trench in the substrate;
forming a silicon oxide trench fill layer to at least fill the isolation trench in the substrate;
removing a portion of the silicon oxide trench fill layer in the isolation trench in the substrate to expose a sidewall of the isolation trench in the substrate without exposing a bottom of the isolation trench in the substrate;
forming a gate dielectric layer over the substrate; and
forming a gate electrode layer over the substrate to fill an empty portion of the isolation trench in the substrate.
2. The method of claim 1 , further comprising:
forming a pad oxide layer over the substrate.
3. The method of claim 2 , further comprising:
forming a nitride layer over the pad oxide layer.
4. The method of claim 3 , wherein the formation of the isolation trench in the substrate comprises:
defining an isolation trench in the nitride layer, the pad oxide layer and the substrate.
5. The method of claim 4 , further comprising:
forming a silicon oxide trench liner layer into the isolation trench in the substrate.
6. The method of claim 1 , wherein the formation of the silicon oxide trench fill layer comprises:
forming the silicon oxide trench fill layer through an ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) method.
7. The method of claim 1 , wherein the removing the portion of the silicon oxide trench fill layer in the isolation trench in the substrate comprises:
forming a resist layer on the silicon oxide trench fill layer to cover a portion of the isolation trench in the substrate; and
etching away at least the portion of the silicon oxide trench fill layer in the isolation trench in the substrate.
8. The method of claim 1 , further comprising:
performing a planarizing process to the remaining silicon oxide trench fill layer.
9. A method for fabricating a semiconductor structure, comprising:
providing a substrate having a top surface;
forming an isolation trench in the substrate;
forming a silicon oxide trench fill layer to fill the isolation trench in the substrate;
removing a portion of the silicon oxide trench fill layer in the isolation trench in the substrate to expose a sidewall of the isolation trench in the substrate without exposing a bottom of the isolation trench in the substrate;
performing a planarizing process to the remaining silicon oxide trench fill layer; and
forming a gate electrode over the top surface of the substrate to fill an empty portion of the isolation trench in the substrate.
10. The method of claim 9 , wherein a portion of the gate electrode below the top surface of the substrate has a trapezoidal profile in a cross-sectional view.
11. The method of claim 10 , further comprising:
forming a gate dielectric layer over the substrate.
12. The method of claim 11 , wherein the gate dielectric layer extends to a bottom of the portion of the gate electrode below the top surface of the substrate without extending along the bottom.
13. The method of claim 9 , further comprising:
forming a pad oxide layer over the substrate.
14. The method of claim 13 , further comprising:
forming a nitride layer over the pad oxide layer.
15. The method of claim 14 , wherein the formation of the isolation trench in the substrate comprises:
defining an isolation trench in the nitride layer, the pad oxide layer and the substrate.
16. The method of claim 15 , further comprising:
forming a silicon oxide trench liner layer into the isolation trench in the substrate.
17. The method of claim 12 , wherein the formation of the silicon oxide trench fill layer comprises:
forming the silicon oxide trench fill layer through an ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) method.
18. A method for fabricating a semiconductor structure, comprising:
providing a substrate;
forming an adhesive forming and stress reducing layer over the substrate;
forming a polish stop layer over the adhesive forming and stress reducing layer;
forming a first isolation trench and a second isolation trench in the substrate;
forming a silicon oxide trench fill layer to at least fill the first isolation trench and the second isolation trench in the substrate;
removing a portion of the silicon oxide trench fill layer in the first isolation trench in the substrate to expose a sidewall of the isolation trench in the substrate without exposing a bottom of the isolation trench in the substrate;
forming a gate dielectric layer over the substrate; and
forming a gate electrode layer over the substrate to fill an empty portion of the first isolation trench in the substrate.
19. The method of claim 18 , wherein the formation of the first isolation trench and the second isolation trench in the substrate comprises:
defining a first isolation trench and a second isolation trench in the polish stop layer, the adhesive forming and stress reducing layer and the substrate.
20. The method of claim 19 , further comprising:
forming a silicon oxide trench liner layer into the first isolation trench and the second isolation trench in the substrate.