Semiconductor device and method for forming the same
A method includes forming a semiconductor fin on a substrate; forming a dielectric layer over the semiconductor fin; forming a metal gate electrode in the dielectric layer and extending across the semiconductor fin; forming a source/drain regions on the semiconductor fin and on opposite sides of the metal gate electrode; performing a first non-zero bias plasma etching process to the metal gate electrode; after performing the first non-zero bias plasma etching process, performing a first zero bias plasma etching process to the metal gate electrode.
1. A method, comprising:
forming a semiconductor fin on a substrate;
forming a dielectric layer over the semiconductor fin;
forming a metal gate electrode in the dielectric layer and extending across the semiconductor fin;
forming a source/drain regions on the semiconductor fin and on opposite sides of the metal gate electrode;
performing a first non-zero bias plasma etching process to the metal gate electrode; and
after performing the first non-zero bias plasma etching process, performing a first zero bias plasma etching process to the metal gate electrode.
2. The method of claim 1 , further comprising:
after performing the first zero bias plasma etching process to the metal gate electrode, performing a second non-zero bias plasma etching process to the metal gate electrode.
3. The method of claim 2 , further comprising:
after performing the second non-zero bias plasma etching process, performing a second zero bias plasma etching process to the metal gate electrode.
4. The method of claim 1 , further comprising:
before performing the first non-zero bias plasma etching process, performing a second zero bias plasma etching process to the metal gate electrode.
5. The method of claim 1 , wherein the first non-zero bias plasma etching process is performed with a bias in a range from about 25V to about 1200V.
6. The method of claim 1 , wherein the first non-zero bias plasma etching process is performed by using a gas mixture comprising Cl 2 , O 2 , BCl 3 , and Ar.
7. The method of claim 1 , the first non-zero bias plasma etching process is performed by using a gas mixture comprising SCl 4 .
8. The method of claim 1 , wherein the first zero bias plasma etching step process is performed by using a gas mixture comprising BCl 3 and Ar without Cl 2 and O 2 .
9. The method of claim 1 , wherein the first non-zero bias plasma etching process has a less etch rate on a peripheral region of the metal gate electrode than on a central region of the metal gate electrode.
10. The method of claim 1 , wherein the first zero bias plasma etching process has a greater etch rate on a peripheral region of the metal gate electrode than on a central region of the metal gate electrode.
11. A method, comprising:
forming a nanostructured pedestal on a substrate, the nanostructured pedestal having a top surface and opposite side surfaces;
forming a dielectric layer wrapping around the top surface and the opposite side surfaces of the nanostructured pedestal;
forming a metal layer over the dielectric layer;
forming a dielectric cap over the metal layer;
forming doped epitaxial structures on the nanostructured pedestal and sandwiching the dielectric layer, the metal layer, and the dielectric cap;
performing a first zero bias plasma etching process to the dielectric cap; and
after performing the first zero bias plasma etching process, performing a first non-zero bias plasma etching process to the dielectric cap.
12. The method of claim 11 , further comprising:
after performing the first non-zero bias plasma etching process to the dielectric cap, performing a second zero bias plasma etching process to the dielectric cap.
13. The method of claim 12 , further comprising:
after performing the second zero bias plasma etching process to the dielectric cap, performing a second non-zero bias plasma etching process to the dielectric cap.
14. The method of claim 13 , wherein the second non-zero bias plasma etching process is performed with a bias in a range from about 25V to about 1200V.
15. The method of claim 11 , further comprising:
before performing the first zero bias plasma etching process to the dielectric cap, performing a second non-zero bias plasma etching process to the dielectric cap.
16. The method of claim 11 , wherein the dielectric cap is made of silicon nitride.
17. The method of claim 11 , wherein the first non-zero bias plasma etching process is performed with a bias in a range from about 25V to about 1200V.
18. The method of claim 11 , wherein the first non-zero bias plasma etching process is performed by using a gas mixture comprising Cl 2 , O 2 , BCl 3 , and Ar.
19. The method of claim 11 , wherein first non-zero bias plasma etching process is performed by using a gas mixture comprising SCl 4 .
20. The method of claim 11 , wherein the first zero bias plasma etching step process is performed by using a gas mixture comprising BCl 3 and Ar without Cl 2 and O 2 .