Semiconductor device
A semiconductor device includes a substrate, a semiconductor fin, a gate electrode, a pair of gate spacers, a dielectric cap, and a hard mask layer. The semiconductor fin extends upwardly from the substrate. The gate electrode straddles the semiconductor fin. The pair of gate spacers is on opposite sidewalls of the gate electrode. The dielectric cap is atop the gate electrode and laterally between the pair of gate spacers. The hard mask layer is atop the dielectric cap and laterally between the pair of gate spacers. A bottommost position of the hard mask layer is not lower than a topmost position of the dielectric cap.
1. A semiconductor device, comprising:
a substrate;
a semiconductor fin extending upwardly from the substrate;
a gate electrode straddling the semiconductor fin;
a pair of gate spacers on opposite sidewalls of the gate electrode;
a dielectric cap atop the gate electrode and laterally between the pair of gate spacers; and
a hard mask layer covering an entirety of a top surface of the dielectric cap and laterally between the pair of gate spacers, wherein a bottommost position of the hard mask layer is not lower than a topmost position of the dielectric cap, and the hard mask layer is made of a different material than the gate spacers.
2. The semiconductor device of claim 1 , wherein a bottommost position of the dielectric cap is not lower than a topmost position of the gate electrode.
3. The semiconductor device of claim 1 , further comprising a gate dielectric layer lining the gate electrode and having an U-shaped when viewed in a cross section, wherein a topmost end surface of the gate dielectric layer is level with a top surface of the gate electrode.
4. The semiconductor device of claim 1 , further comprising a gate dielectric layer lining the gate electrode and having an U-shaped when viewed in a cross section, wherein a bottommost position of the dielectric cap is not lower than a topmost position of the gate dielectric layer.
5. The semiconductor device of claim 1 , wherein a top surface of the dielectric cap is parallel to a top surface of the gate electrode.
6. The semiconductor device of claim 1 , wherein a top surface of the hard mask layer is level with top surfaces of the pair of gate spacers.
7. The semiconductor device of claim 1 , wherein the hard mask layer comprises metal oxide.
8. The semiconductor device of claim 1 , wherein the dielectric cap comprises silicon nitride.
9. A semiconductor device, comprising:
a substrate;
a semiconductor fin extending above the substrate;
a gate structure across the semiconductor fin;
a gate spacer on a sidewall of the gate structure;
a source/drain epitaxy structure on the semiconductor fin and adjacent to the gate structure; and
a dielectric cap on the gate structure, wherein a distance from a topmost position of the dielectric cap to a bottommost position of the dielectric cap is greater than a distance from a topmost position of the gate structure to a bottommost position of the gate structure, and the dielectric cap has the same width as the gate structure, and a topmost position of the dielectric cap is lower than a topmost position of the gate spacer.
10. The semiconductor device of claim 9 , wherein a topmost position of the dielectric cap is higher than a topmost position of the source/drain epitaxy structure.
11. The semiconductor device of claim 9 , wherein the dielectric cap comprises silicon nitride.
12. The semiconductor device of claim 9 , further comprising a metal oxide layer over the dielectric cap, wherein the metal oxide layer is thinner than the dielectric cap.
13. The semiconductor device of claim 9 , further comprising a metal oxide layer over the dielectric cap, wherein the metal oxide layer has the same width as the gate structure.
14. A semiconductor device, comprising:
a substrate;
a semiconductor fin on the substrate;
a pair of gate spacers above the semiconductor fin;
a gate electrode laterally between the pair of gate spacers;
a gate dielectric layer lining the gate electrode and having an U-shaped when viewed in a cross section;
a silicon nitride layer over the gate electrode and the gate dielectric layer; and
a metal oxide layer over the silicon nitride layer and having a top surface level with top surfaces of the gate spacers, the metal oxide layer horizontally extending from a first one of the pair of gate spacers to a second one of the pair of gate spacers.
15. The semiconductor device of claim 14 , wherein an interface between the silicon nitride layer and the gate dielectric layer is at the same level with an interface between the silicon nitride layer and the gate electrode.
16. The semiconductor device of claim 14 , wherein the gate dielectric layer comprises a hafnium-containing material.
17. The semiconductor device of claim 14 , wherein the gate dielectric layer comprises a zirconium-containing material.
18. The semiconductor device of claim 9 , further comprising:
a metal oxide layer over the dielectric cap and having a same width as the dielectric cap.
19. The semiconductor device of claim 1 , wherein the hard mask layer has a same width as the dielectric cap along a lengthwise direction of the semiconductor fin.
20. The semiconductor device of claim 9 , further comprising a metal oxide layer over the dielectric cap, wherein a vertical interface formed by the gate spacer and the dielectric cap is coterminous with a vertical interface formed by the gate spacer and the metal oxide layer.