Absorption enhancement structure for image sensor
The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a substrate and an image sensing element disposed within the substrate. The substrate has sidewalls defining a plurality of protrusions over the image sensing element. A first one of the plurality of protrusions including a first sidewall having a first segment. A line that extends along the first segment intersects a second sidewall of the first one of the plurality of protrusions that opposes the first sidewall.
1. An image sensor integrated chip, comprising:
a substrate;
an image sensing element disposed within the substrate;
wherein the substrate has sidewalls defining a plurality of protrusions over the image sensing element, a first one of the plurality of protrusions comprising a first sidewall having a first segment; and
wherein a line that extends along the first segment intersects a second sidewall of the first one of the plurality of protrusions that opposes the first sidewall.
2. The integrated chip of claim 1 ,
wherein the plurality of protrusions are disposed along a first side of the substrate;
wherein a second side of the substrate, which opposes the first side, has a slope of zero;
wherein the first segment has a first slope; and
wherein the first sidewall further comprises a second segment disposed over the first segment, the second segment having a second slope that is larger than the first slope.
3. The integrated chip of claim 1 , further comprising:
a dielectric material arranged on and between the plurality of protrusions, wherein the dielectric material has an upper surface disposed completely over the plurality of protrusions.
4. The integrated chip of claim 1 ,
wherein the first sidewall has a second segment between the first segment and a top of the first one of the plurality of protrusions; and
wherein the first segment is linear and the second segment is curved as viewed in a cross-sectional view.
5. The integrated chip of claim 1 ,
wherein the first sidewall has a second segment between the first segment and a top of the first one of the plurality of protrusions; and
wherein the first segment has a constant slope and the second segment has a slope that changes as viewed in a cross-sectional view.
6. The integrated chip of claim 1 , wherein the plurality of protrusions respectively have a height and a width, an aspect ratio between the height and the width is in a range of between approximately 1 and approximately 1.25.
7. The integrated chip of claim 1 , wherein the first segment of the first sidewall is devoid of plasma damage.
8. The integrated chip of claim 1 , wherein the plurality of protrusions respectively have a height that is in a range of between approximately 400 nm and approximately 600 nm.
9. An integrated chip, comprising:
a substrate comprising a first plurality of sidewalls defining a plurality of protrusions along a first side of the substrate and further comprising a second plurality of sidewalls defining a ridge along the first side of the substrate, the ridge surrounding a pixel region of the substrate;
an image sensing element disposed within the pixel region of the substrate; and
wherein a horizontal plane that extends along an upper surface of the substrate defining the ridge is vertically separated from tops of the plurality of protrusions by one or more non-zero distances, the horizontal plane parallel to the upper surface.
10. The integrated chip of claim 9 , wherein the ridge has a height that is in a range of between approximately 5% and approximately 15% larger than heights of the plurality of protrusions.
11. The integrated chip of claim 9 , wherein the ridge has a height that is in a range of between approximately 500 nm and approximately 600 nm.
12. The integrated chip of claim 9 , wherein the plurality of protrusions are arranged within the pixel region in rows extending along a first direction and in columns extending along a second direction that is perpendicular to the first direction.
13. The integrated chip of claim 9 , wherein the plurality of protrusions within the pixel region consists of four rows and four columns of protrusions.
14. The integrated chip of claim 9 , wherein an isolation structure is arranged along the upper surface of the substrate defining the ridge and comprises a dielectric material disposed within the substrate.
15. An integrated chip, comprising:
a substrate comprising a plurality of sidewalls defining a first protrusion and a second protrusion disposed along a first side of the substrate;
an image sensing element arranged within the substrate; and
wherein the first protrusion comprises a first sidewall having a first flat segment and the second protrusion comprises a second sidewall having a second flat segment, the first flat segment is coupled to the second flat segment by a horizontally extending surface of the substrate that is between the first protrusion and the second protrusion.
16. The integrated chip of claim 15 , wherein the first flat segment of the first sidewall is devoid of plasma damage.
17. The integrated chip of claim 15 , wherein the first flat segment of the first sidewall extends along a crystalline plane.
18. The integrated chip of claim 15 , further comprising:
one or more absorption enhancement layers contacting the first flat segment of the first sidewall, the second flat segment of the second sidewall, and the horizontally extending surface of the substrate.
19. The integrated chip of claim 18 , wherein the one or more absorption enhancement layers comprise silicon dioxide.
20. The integrated chip of claim 15 , wherein the substrate is a semiconductor material.