Semiconductor structure and associated fabricating method
View Patent ↗A process for fabricating a semiconductor structure is disclosed. The process includes: forming an isolation trench in a substrate; forming a trench fill layer to at least fill the isolation trench in the substrate, the silicon oxide trench fill layer comprising a portion in contact with the substrate below an upper surface of the substrate; exposing a sidewall of the isolation trench and without exposing a bottom of the isolation trench in the substrate; and forming a gate structure over the substrate, wherein the gate structure contacts the sidewall of the isolation trench.
1. A method for fabricating a semiconductor structure, comprising:
forming an isolation trench in a substrate;
forming a silicon oxide trench fill layer to at least fill the isolation trench in the substrate, the silicon oxide trench fill layer comprising a first portion in the isolation trench;
removing a second portion of the first portion of the silicon oxide trench fill layer in the isolation trench, without exposing a bottom of the isolation trench in the substrate;
forming a first well region in the substrate that includes the isolation trench, the first well region having a first conductivity type and wherein the first portion of the silicon oxide trench fill layer contacts the first well region; and
forming a gate structure over the substrate, wherein the gate structure contacts the first well region of the substrate and fills an empty portion of the isolation trench in the first well region of the substrate created by removing the second portion.
2. The method of claim 1 , further comprising:
forming a pad oxide layer over the substrate.
3. The method of claim 2 , further comprising:
forming a nitride layer over the pad oxide layer.
4. The method of claim 3 , wherein the formation of the isolation trench in the substrate comprises:
defining an isolation trench in the nitride layer, the pad oxide layer and the substrate.
5. The method of claim 1 wherein forming the silicon oxide trench fill layer comprises forming a liner layer lining the isolation trench in the well region of the substrate.
6. The method of claim 1 , wherein the formation of the silicon oxide trench fill layer comprises:
forming the silicon oxide trench fill layer through an ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) method.
7. The method of claim 1 , wherein removing the second portion of the trench fill layer comprises:
forming a resist layer on the silicon oxide trench fill layer to cover a portion of the isolation trench in the substrate; and
etching away at least the portion of the silicon oxide trench fill layer in the isolation trench in the substrate.
8. The method of claim 1 , wherein the formation of the gate structure comprises:
forming a gate dielectric layer on an upper surface of the substrate and on a part of a sidewall of the isolation trench; and
forming a gate electrode layer over the substrate, wherein the gate electrode layer fills a remaining empty space of the isolation trench.
9. A method for fabricating a semiconductor structure, comprising:
forming an isolation trench in a substrate;
forming a silicon oxide trench fill layer in the isolation trench;
removing a portion of the silicon oxide trench fill layer in the isolation trench without exposing a bottom surface of the isolation trench in the substrate;
forming a first well region in the substrate that includes the isolation trench, the first well region having a first conductivity type, and wherein the silicon oxide trench fill layer is in contact with the first well region in the isolation trench; and
forming a gate structure over the substrate to fill an empty portion of the isolation trench in the substrate created when the portion of the silicon oxide trench fill layer was removed, wherein the gate structure is formed over the first well region and a second well region of the substrate, the second well region having a second conductivity type different from the first conductivity type, and wherein the gate structure contacts the first well region of the substrate.
10. The method of claim 9 , wherein the isolation trench and the gate structure are disposed between source and drain regions of a transistor.
11. The method of claim 9 wherein forming the gate structure comprises
forming a gate dielectric layer over the substrate; and
forming a gate electrode over the gate dielectric layer.
12. The method of claim 9 further comprising planarizing the silicon oxide trench fill layer.
13. The method of claim 9 further comprising forming source and drain structures in the substrate on opposing sides of the gate structure and the isolation trench.
14. The method of claim 9 , further comprising:
forming a pad oxide layer over the substrate; and
forming a nitride layer over the pad oxide layer.
15. The method of claim 14 , wherein the formation of the isolation trench in the substrate comprises:
defining an isolation trench in the nitride layer, the pad oxide layer and the substrate.
16. The method of claim 9 , wherein forming the silicon oxide trench fill layer comprises
forming a liner layer lining the isolation trench in the substrate.
17. The method of claim 9 , wherein the formation of the silicon oxide trench fill layer comprises:
forming the silicon oxide trench fill layer through an ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) method.
18. A method for fabricating a semiconductor structure, comprising:
forming a first isolation trench and a second isolation trench in a substrate;
forming a trench fill layer to at least fill the first isolation trench and the second isolation trench in the substrate;
removing a second portion of the silicon oxide trench fill layer in the first isolation trench without exposing a bottom of the first isolation trench in the substrate;
forming first and second well regions in the substrate, wherein the first well region includes the first isolation trench and the second well region includes the second isolation trench; wherein the second well region has a conductivity type different from the first well region; and
forming a gate structure over the substrate to fill an empty portion of the first isolation trench in the substrate created when the second portion was removed, wherein the gate structure contacts the first well region of the substrate.
19. The method of claim 18 , wherein the first isolation trench and the gate electrode are disposed between source and drain regions of the substrate.
20. The method of claim 18 , wherein the gate structure is formed over the first and second well regions.