Metal gate finFET device and method of fabricating thereof

1. A method, comprising:

providing a substrate having a fin extending therefrom, wherein a shallow trench isolation (STI) feature is disposed adjacent the fin and the fin extends a fin height above the STI feature; and

forming a metal gate structure on the fin, wherein the forming the metal gate structure includes:

forming a stress metal layer on the fin such that the stress metal layer extends to a first height above the STI feature, the first height being greater than the fin height, wherein the forming the stress metal layer includes:

depositing a stress metal on the substrate including in a trench;

forming a layer on the deposited stress metal including a first portion outside the trench and a second potion in the trench;

performing a polishing process to remove the first portion of the layer; and

etching the deposited stress metal using the second portion of the layer as a masking element; and

forming a conduction metal layer on the stress metal layer after etching the deposited stress metal.

2. The method of claim 1 , wherein the stress metal layer is formed on a top surface of the fin, the top surface substantially parallel to a top surface of the substrate.

3. The method of claim 1 , wherein the stress metal layer is formed directly on a gate dielectric layer.

4. The method of claim 1 , wherein the stress metal layer and the conduction metal layer are formed in the trench provided by removing a dummy gate structure.

5. The method of claim 1 , wherein the etching the deposited stress metal includes removing the stress metal disposed outside of the trench.

6. The method of claim 1 , further comprising:

removing the second portion of the layer before forming the conduction metal layer.

7. The method of claim 1 , wherein the stress metal layer includes a metal selected from the group consisting of W, TiN, TaN, WN, Re, Ir, Ru, Mo, and combinations thereof.

8. The method of claim 1 , wherein the conduction metal layer includes a metal selected from the group consisting of Al, Cu, CO, Ni, and combinations thereof.

9. A method of fabricating a semiconductor device, comprising:

providing a substrate having a fin element and an isolation feature, wherein the fin element extends a height of H fin above a top surface of the isolation feature;

forming a metal gate structure in a trench provided by a removal of a dummy gate structure formed on the fin element, wherein the forming the metal gate structure includes:

forming a first metal layer in the trench, wherein the first metal layer has a height Hsm above the top surface of the isolation feature;

forming a photosensitive layer on the first metal layer;

performing a chemical mechanical polish (CMP) process to remove the photosensitive layer disposed outside of the trench and form a polished photosensitive layer disposed in the trench;

etching the first metal layer using the polished photosensitive layer as a masking element; and

forming a second metal layer in the trench on the etched first metal layer.

10. The method of claim 9 , wherein the second metal layer has a thickness H con and wherein H fin <H sm <(H fin +(H gate /2));

wherein H gate is a sum of H con and (H sm −H fin ).

11. The method of claim 9 , further comprising:

forming the dummy gate structure including a dummy polysilicon layer on the fin; and

forming a dielectric layer adjacent the polysilicon layer; and

etching the polysilicon layer to form the trench.

12. The method of claim 9 , wherein the etching the first metal layer using the polished photosensitive layer as a masking element includes removing the first metal layer from a region outside of the trench; and

after the etching, stripping the polished photosensitive layer prior to forming the second metal layer.

13. The method of claim 9 , wherein the forming the first metal layer includes forming a conformal layer of a metal selected from the group consisting of W, TiN, TaN, WN, Re, Ir, Ru, Mo, and combinations thereof.

14. The method of claim 1 , wherein the layer is a photosensitive layer.

15. A method of fabricating a finFET semiconductor device, comprising:

providing a substrate having a fin element, wherein the fin element extends a height of H fin ;

forming a trench on and around the fin element;

forming a gate dielectric layer in the trench;

forming a first metal layer in the trench on the gate dielectric layer, wherein the first metal layer has a height H sm above the top surface of the isolation feature, wherein the forming the first metal layer leaves an opening in the trench;

forming a protective layer on the first metal layer in the opening in the trench;

etching the first metal layer using the protective layer in the opening of the trench as a masking element; and

forming a second metal layer in the trench on the etched first metal layer, wherein the second metal has a thickness H con .

16. The method of claim 15 , wherein H fin <H sm <(H fin +(H gate /2));

wherein H gate is a sum of H con and (H sm −H fin ).

17. The method of claim 15 , wherein the forming the protective layer includes depositing a photoresist layer.

18. The method of claim 17 , wherein the forming the protective layer further includes:

depositing the photoresist layer in the opening in the trench and outside of the trench; and

performing a planarization process to remove the deposited photoresist layer from outside of the trench.