Integrated semiconductor structure for SRAM and fabrication methods thereof
View Patent ↗A SRAM device with metal gate transistors is provided. The SRAM device includes a PMOS structure and an NMOS structure over a substrate. Each of the PMOS and the NMOS structure includes a p-type metallic work function layer and an n-type metallic work function layer. The p-type work metallic function layer and the n-type metallic work function layer form a combined work function for the PMOS and the NMOS structures.
1. A semiconductor device comprising:
a NMOS structure, comprising, a first gate dielectric overlying a substrate; and a first metal gate overlying the first gate dielectric; and
a PMOS structure, comprising, a second gate dielectric overlying the substrate; and a second metal gate overlying the second gate dielectric,
wherein the work function of the first metal gate and the second metal gate is a combined work function resulted by a p-type work function and an n-type work function.
2. The semiconductor device of claim 1 , wherein the device is static random access memory (SRAM).
3. The semiconductor device of claim 1 , wherein the first metal gate and the second metal gate each has a work function ranging between about 4.4 eV and about 4.8 eV.
4. The semiconductor device of claim 3 , wherein the work function is about 4.6 eV.
5. The semiconductor device of claim 1 , wherein the first metal gate comprises a first p-type work function layer and a first n-type work function layer and the second metal gate comprises a second p-type work function layer and a second n-type work function layer.
6. The semiconductor device of claim 5 , wherein the first p-type work function layer is the same as the second p-type work function layer and the first n-type work function layer is the same as the second n-type work function layer.
7. The semiconductor device of claim 5 , wherein the first p-type work function layer and the second p-type work function layer each has a work function not less than 4.8 eV, the first n-type work function layer and the second n-type work function layer each has a work function not larger than 4.4 eV.
8. The semiconductor device of claim 5 , wherein the first and the second p-type work function layers are titanium nitride, tantalum nitride, or cobalt.
9. The semiconductor device of claim 5 , wherein the first and the second n-type work function layers are titanium, tantalum, aluminum, titanium alloy, tantalum alloy, or aluminum alloy.
10. The semiconductor device of claim 1 wherein:
the first metal gate includes a first metal layer disposed over the first gate dielectric and a second metal layer disposed over the first metal layer;
the second metal gate includes a third metal layer disposed over the second gate dielectric and a fourth metal layer disposed over the third metal layer, the first metal layer and the third metal layer including a same material and the second metal layer and the fourth metal layer including a same material.
11. The semiconductor device of claim 10 wherein:
the first metal layer and the third metal layer are p-type work function layers; and
the second metal layer and the fourth metal layer are n-type work function layers.
12. The semiconductor device of claim 10 wherein the same material of the first metal layer and the third metal layer is titanium nitride, tantalum nitride, cobalt, or combinations thereof.
13. The semiconductor device of claim 10 wherein the same material of the second metal layer and the fourth metal layer is titanium, tantalum, aluminum, or combinations thereof.
14. The semiconductor device of claim 1 wherein the NMOS structure is a portion of a SRAM device and the PMOS structure is a portion of a logic device.
15. A device comprising:
an NMOS transistor that includes:
a first gate dielectric layer disposed over a substrate, and
a first metal gate disposed over the first gate dielectric layer, wherein the first metal gate has a first work function that results from a combined p-type work function and n-type work function; and
a PMOS transistor that includes:
a second gate dielectric layer disposed over the substrate, and
a second metal gate disposed over the second gate dielectric layer, wherein the second metal gate has a second work function that results from a combined p-type work function and n-type work function.
16. The device of claim 15 wherein the first work function and the second work function range from about 4.4 eV to about 4.8 eV.
17. The device of claim 15 wherein the first work function and the second work function are about 4.6 eV.
18. The device of claim 15 wherein the NMOS transistor and the PMOS transistor are a portion of a SRAM cell.
19. The device of claim 18 further including a CMOS cell, wherein the CMOS cell includes:
another NMOS transistor that includes:
a third gate dielectric layer disposed over a substrate, and
a third metal gate disposed over the third gate dielectric layer, wherein the third metal gate has a third work function; and
another PMOS transistor that includes:
a fourth gate dielectric layer disposed over the substrate, and
a fourth metal gate disposed over the fourth gate dielectric layer, wherein the fourth metal gate has a fourth work function that results from a combined p-type work function and n-type work function.
20. The device of claim 19 wherein:
the first work function is equal to the second work function; and
the third work function is different than the fourth work function.