Semiconductor structure and method for forming the same
A semiconductor structure includes a first FET device, a second FET device disposed, and an isolation separating the first FET device and the second FET device. The first FET device includes a fin structure, a first work function metal layer disposed over the fin structure, and a high-k gate dielectric layer between the first work function metal layer and the fin structure. The second FET device includes a plurality of nanosheets separated from each other, a second work function metal layer surrounding each of the nanosheets, and the high-k gate dielectric layer between the second work function metal layer and each of the nanosheets. A portion of the high-k gate dielectric layer is directly over the isolation.
1. A semiconductor structure comprising:
a first field effect transistor (PET) device comprising:
a fin structure;
a first work function metal layer over the fin structure; and
a high-k gate dielectric layer between the first work function metal layer and the fin structure;
a second PET device comprising:
a plurality of nanosheets separated from each other;
a second work function metal layer surrounding each of the nanosheets;
a third work function metal layer surrounding the second work function metal layer; and
the high-k gate dielectric layer between the second work function metal layer and each of the nanosheets; and
an isolation separating the first PET device and the second PET device,
wherein a portion of the high-k gate dielectric layer is directly over the isolation,
wherein the second work function metal layer is an n-type work function metal layer, and
the third work function metal layer is a p-type work function metal layer.
2. The semiconductor structure of claim 1 , wherein the first work function metal layer is a p-type work function metal layer.
3. The semiconductor structure of claim 1 , wherein a thickness of the third work function metal layer is equal to or greater than a thickness of the first work function metal layer.
4. The semiconductor structure of claim 1 , wherein the first work function metal layer is an n-type work function metal layer.
5. The semiconductor structure of claim 4 , wherein the second FET device further comprises a fourth work function metal layer on the third work function metal layer, and the fourth work function metal layer is a same material as the first work function metal layer.
6. The semiconductor structure of claim 1 , wherein the high-k gate dielectric layer is in contact with the isolation.
7. The semiconductor structure of claim 1 , wherein a crystal plane of each of the nanosheets is a (100) plane.
8. A semiconductor structure, comprising:
a first fin structure, a second fin structure, and a third fin structure separated from each other;
a plurality of nanosheets separated from the first fin structure, the second fin structure and the third fin structure;
a high-k gate dielectric layer over each of the first fin structure, the second fin structure and third fin structure, and surrounding each of the nanosheets;
a first work function metal layer over the high-k gate dielectric layer and the first fin structure;
a second work function metal layer over the high-k gate dielectric layer and the second fin structure;
a third work function metal layer over the high-k gate dielectric layer and the third fin structure; and
a fourth work function metal layer over the high-k gate dielectric layer and surrounding each of the nanosheets.
9. The semiconductor structure of claim 8 , wherein the first work function metal layer and the fourth work function metal layer are n-type work function metal layers.
10. The semiconductor structure of claim 9 , wherein the first work function metal layer is different from the fourth work function metal layer.
11. The semiconductor structure of claim 10 , further comprising a fifth work function metal layer over the fourth work function metal layer and the plurality of nanosheets, wherein the fifth work function metal layer and the first work function metal layer are the same.
12. The semiconductor structure of claim 8 , wherein the second work function metal layer and the third work function metal layer are p-type work function metal layers.
13. The semiconductor structure of claim 12 , wherein the second work function metal layer is different from the third work function metal layer.
14. The semiconductor structure of claim 12 , further comprising a sixth work function metal layer over the fourth work function metal layer and the plurality of nanosheets, wherein the sixth work function metal layer and the third work function metal layer are the same.
15. The semiconductor structure of claim 8 , wherein a crystal plane of each of the nanosheets is a (100) plane.
16. A method for forming a semiconductor structure, comprising:
forming a first fin structure, a second fin structure, a third fin structure and a nanosheet stack over a substrate, wherein the nanosheet stack comprises a plurality of nanosheets separated from each other;
forming a high-k gate dielectric layer over the first fin structure, the second fin structure and the third fin structure, and surrounding each of the nanosheets;
forming a first work function metal layer to surround each of the nanosheets;
forming a first passivation layer to wrap each of the nanosheets; and
forming a second work function metal layer to cover the first fin structure, the third fin structure and the nanosheet stack,
wherein the first work function metal layer is complementary to the second work function metal layer.
17. The method of claim 16 , further comprising:
forming a third work function metal layer to cover the second fin structure, the third fin structure and the nanosheet stack; and
forming a fourth work function metal layer to cover the first fin structure, the second fin structure, the third fin structure and the nanosheet stack,
wherein the third work function metal layer is complementary to the fourth work function metal layer.
18. The method of claim 16 , wherein the forming of the second work function metal layer to cover the first fin structure, the third fin structure and the nanosheet stack further comprises:
forming the second work function metal layer to cover the first fin structure, the second fin structure, the third fin structure and the nanosheet stack; and
removing a portion of the second work function metal layer to expose the high-k gate dielectric layer over the second fin structure.
19. The method of claim 17 , wherein the forming of the third work function metal layer to cover the second fin structure, the third fin structure and the nanosheet stack further comprises:
forming the third work function metal layer to cover the first fin structure, the second fin structure, the third fin structure and the nanosheet stack; and
removing a portion of the third work function metal layer to expose the high-k gate dielectric layer over the first fin structure.
20. The method of claim 16 , further comprising forming a second passivation layer to cover the first fin structure, the second fin structure, the third fin structure and the nanosheet stack.