IP Library Granted Patent US 11,043,410
Granted Patent B2
US 11,043,410 · App. 16/829,295 · Granted Jun 22, 2021

Packages with through-vias having tapered ends

Inventor: Hsien-Wei Chen (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L21/76804H01L21/6835H01L24/19H01L24/20H01L24/24H01L24/82H01L25/105H01L25/50H01L21/561H01L21/568H01L23/3128H01L24/29H01L24/32H01L24/48H01L24/73H01L24/83H01L24/92H01L2221/68372H01L2224/04042H01L2224/04105H01L2224/12105H01L2224/19H01L2224/2919H01L2224/32225H01L2224/45015H01L2224/48091H01L2224/48227H01L2224/73265H01L2224/73267H01L2224/83005H01L2224/92244H01L2225/1035H01L2225/1041H01L2225/1058H01L2924/00014H01L2924/15311H01L2924/181
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Quick Facts
Patent No.
US 11,043,410
App. No.
16/829,295
Granted
Jun 22, 2021
Kind
B2
Abstract

A package includes a device die, a molding material molding the device die therein, a through-via substantially penetrating through the molding material, wherein the through-via has an end. The end of the through-via is tapered and has rounded sidewall surfaces. The package further includes a redistribution line electrically coupled to the through-via.

Claims (40)

1. A method comprising:

forming a conductive post over a carrier;

placing a device die over the carrier;

encapsulating the device die and the conductive post in an encapsulant;

planarizing the encapsulant to expose the conductive post;

after the encapsulant is planarized, etching the conductive post so that the conductive post is recessed into the encapsulant, wherein after the etching, a first top surface of the conductive post is rounded; and

forming a conductive feature over and contacting the conductive post.

2. The method of claim 1 , wherein the device die comprises metal pillars at a second top surface of the device die, and wherein after the etching, the metal pillars of the device die have top surfaces higher than a top surface of the conductive post.

3. The method of claim 1 , wherein the device die comprises metal pillars at a second top surface of the device die, and wherein during the etching, the metal pillars of the device die are not etched.

4. The method of claim 1 further comprising:

forming a dielectric layer over the encapsulant, wherein the dielectric layer comprises a portion extending into a recess formed by the etching the conductive post.

5. The method of claim 4 further comprising:

forming a conductive via extending into the dielectric layer, wherein the via further extends into the recess to contact the conductive post.

6. The method of claim 5 , wherein the etching the conductive post comprises a wet etching process.

7. The method of claim 1 , wherein the forming the conductive post comprises plating the conductive post over the carrier.

8. A method comprising:

forming a patterned photo resist;

plating a conductive post in the patterned photo resist;

removing the patterned photo resist;

encapsulating the conductive post in an encapsulating material;

performing a planarization on the encapsulating material to reveal the conductive post;

etching the conductive post so that the conductive post has a tapered top end; and

forming a redistribution line over and in contact with the conductive post.

9. The method of claim 8 , wherein after the planarization and before the etching, the conductive post has a planar top surface.

10. The method of claim 8 , wherein the etching the conductive post comprises a wet etching process.

11. The method of claim 8 , wherein the redistribution line comprises a via extending into a recess formed in the encapsulant, wherein the recess is formed by the etching the conductive post.

12. The method of claim 8 further comprising forming a dielectric layer over and contacting the encapsulating material, wherein the dielectric layer comprises a lower portion extending into the encapsulating material, and the via extends into the lower portion of the dielectric layer.

13. The method of claim 8 , wherein after the etching the conductive post, the tapered top end of the conductive post is lower than a flat top surface of the encapsulant.

14. The method of claim 8 further comprises encapsulating a device die in the encapsulant, wherein the device die comprises a metal pillar, with the metal pillar exposed after the planarization, and wherein in the etching, the metal pillar is un-etched.

15. A method comprising:

forming a conductive post over a carrier;

placing a device die over the carrier, wherein the device die comprises a metal pillar as a top feature of the device die;

encapsulating the conductive post and the device die in an encapsulating material, wherein the conductive post is in the encapsulating material;

after the encapsulating, performing an etching process, and wherein after the etching process, the conductive post is exposed through the encapsulating material and has a first top surface lower than a second top surface of the metal pillar; and

forming a redistribution line over and in contact with the conductive post.

16. The method of claim 15 , wherein after the etching process, the second top surface of the metal pillar is coplanar with a third top surface of the encapsulant.

17. The method of claim 15 , wherein the etching process comprises etching the conductive post.

18. The method of claim 15 , wherein the etching process comprises etching the encapsulating material.

19. The method of claim 15 , wherein a lower portion of the conductive post has straight edges.

20. The method of claim 1 , wherein after the etching, the rounded top surface of the conductive post is connected to straight sidewalls of the conductive post.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 5, 2024
From: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
To: PARABELLUM STRATEGIC OPPORTUNITIES FUND LLC
Reel/Frame 068326/0474 →
Continuity (4)
Continuation 16035910 · Jul 16, 2018
Continuation 15668315 · Aug 3, 2017
Division 14206248 · Mar 12, 2014
Related Publication 20200227310A1 · Jul 16, 2020
Cited By (1)
US 12,575,435