Semiconductor device including a liner layer between a channel and a source/drain epitaxial layer
A semiconductor device includes first channel layers disposed over a substrate, a first source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the first channel layers, a gate electrode layer disposed on the gate dielectric layer and wrapping each of the first channel layers, and a liner semiconductor layer disposed between the first channel layers and the first source/drain region.
1. A semiconductor device, comprising:
first channel layers disposed over a bottom fin structure protruding from a substrate;
a gate dielectric layer disposed on and wrapping each of the first channel layers;
a gate electrode layer disposed on the gate dielectric layer;
sidewall spacers disposed on opposing side faces of the gate electrode layer;
a source/drain epitaxial layer; and
a liner semiconductor layer disposed between the first channel layers and the source/drain epitaxial layer, wherein:
a length of the first channel layers is smaller than a distance between vertical outer surfaces of the sidewall spacers,
the liner semiconductor layer is in direct contact with vertical end faces of the first channel layers, and
the liner semiconductor layer includes first portions disposed between adjacent first channel layers in a vertical direction and a second portion connecting the first portions.
2. The semiconductor device of claim 1 , wherein the liner semiconductor layer includes a third portion extending from the second portion and disposed on an upper surface of the bottom fin structure.
3. The semiconductor device of claim 2 , further comprising an isolation insulating layer covering sides of the bottom fin structure,
wherein the upper surface of the bottom fin structure on which the third portion of the liner semiconductor layer is disposed is located below an upper surface of the isolation insulating layer.
4. The semiconductor device of claim 1 , wherein the source/drain epitaxial layer is not in contact with the first channel layers.
5. The semiconductor device of claim 1 , wherein the first channel layers are made of Si or a Si-based compound.
6. The semiconductor device of claim 1 , wherein the liner semiconductor layer is made of Si or a Si-based compound.
7. The semiconductor device of claim 1 , wherein the liner semiconductor layer is disposed between the gate electrode layer and the source/drain epitaxial layer in a horizontal direction along which the first channel layer extends.
8. A semiconductor device, comprising:
first channel layers disposed over a bottom fin structure protruding from a substrate;
second channel layers disposed over the bottom fin structure;
a first gate dielectric layer disposed on and wrapping each of the first channel layers, and a first gate electrode layer disposed on the first gate dielectric layer;
a second gate dielectric layer disposed on and wrapping each of the second channel layers, and a second gate electrode layer disposed on the second gate dielectric layer;
a source/drain epitaxial layer disposed between the first channel layers and the second channel layers; and
a liner semiconductor layer disposed between the first channel layers and the source/drain epitaxial layer and between the second channel layers and the source/drain epitaxial layer, wherein:
vertical end surfaces of the first channel layers face vertical end surfaces of the second channel layers, and
the liner semiconductor layer covers the vertical end surfaces of the first channel layers and the vertical end surfaces of the second channel layers.
9. The semiconductor device of claim 8 , wherein the liner semiconductor layer includes:
first portions disposed between adjacent first channel layers in a vertical direction;
second portions connecting the first portions;
third portions disposed between adjacent second channel layers in the vertical direction; and
fourth portions connecting the third portions.
10. The semiconductor device of claim 9 , wherein the liner semiconductor layer includes a fifth portion connecting the second portion and the fourth portion and disposed on an upper surface of the bottom fin structure.
11. The semiconductor device of claim 8 , wherein the source/drain epitaxial layer is not in contact with the first channel layers.
12. The semiconductor device of claim 8 , wherein:
the first channel layers are made of Si or a Si-based compound, and
the liner semiconductor layer is made of Si or a Si-based compound.
13. The semiconductor device of claim 8 , wherein the liner semiconductor layer is disposed on the bottom fin structure.
14. A semiconductor device, comprising:
first channel layers disposed over a bottom fin structure protruding from a substrate;
a gate dielectric layer disposed on and wrapping each of the first channel layers;
a gate electrode layer disposed on the gate dielectric layer;
sidewall spacers disposed on opposing side faces of the gate electrode layer;
a source/drain epitaxial layer;
a liner semiconductor layer disposed between the first channel layers and the source/drain epitaxial layer; and
a conductive material layer in contact with the source/drain epitaxial layer, wherein:
the liner semiconductor layer is in contact with vertical end faces of the first channel layers and is continuously formed to directly connect the first channel layers, and
the conductive material layer penetrates into the source/drain epitaxial layer.
15. The semiconductor device of claim 14 , wherein the conductive material layer includes a silicide layer in contact with the source/drain epitaxial layer and a conductive material layer disposed on the silicide layer.
16. The semiconductor device of claim 14 , wherein the silicide layer is separated from the liner semiconductor layer by the source/drain epitaxial layer.
17. The semiconductor device of claim 14 , wherein:
the liner semiconductor layer includes first portions disposed between adjacent first channel layers in a vertical direction, a second portion connecting the first portions, and a third portion extending from the second portion and disposed on an upper surface of the bottom fin structure.
18. The semiconductor device of claim 17 , further comprising an isolation insulating layer covering sides of the bottom fin structure,
wherein the upper surface of the bottom fin structure on which the third portion of the liner semiconductor layer is disposed is located below an upper surface of the isolation insulating layer.
19. The semiconductor device of claim 17 , wherein the source/drain epitaxial layer is not in contact with the first channel layers.
20. The semiconductor device of claim 17 , wherein the liner semiconductor layer is disposed between the gate electrode layer and the source/drain epitaxial layer in a horizontal direction along which the first channel layer extends.