IP Library Granted Patent US 8,525,270
Granted Patent B2
US 8,525,270 · App. 12/713,395 · Granted Sep 3, 2013

Structures and methods to stop contact metal from extruding into replacement gates

Inventors: Lee-Wee Teo (Singapore, SG); Ming Zhu (Singapore, SG); Chi-Ju Lee (Gurien Township, TW); Sheng-Chen Chung (Jhubei, TW); Kai-Shyang You (Jhubei, TW); Harry-Hak-Lay Chuang (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,525,270
App. No.
12/713,395
Granted
Sep 3, 2013
Kind
B2
Abstract

The methods and structures described are used to prevent protrusion of contact metal (such as W) horizontally into gate stacks of neighboring devices to affect the work functions of these neighboring devices. The metal gate under contact plugs that are adjacent to devices and share the (or are connected to) metal gate is defined and lined with a work function layer that has good step coverage to prevent contact metal from extruding into gate stacks of neighboring devices. Only modification to the mask layout for the photomask(s) used for removing dummy polysilicon is involved. No additional lithographical operation or mask is needed. Therefore, no modification to the manufacturing processes or additional substrate processing steps (or operations) is involved or required. The benefits of using the methods and structures described above may include increased device yield and performance.

Claims (30)

1. An integrated circuit structure comprising:

a gate structure with a first gate stack including a gate metal layer having a void; and

a contact plug filled with a contact metal, wherein the contact metal protrudes into the void and the contact plug is disposed directly on the gate metal layer of the first gate stack, and the gate metal layer underneath the contact plug is surrounded by a work function layer to prevent the contact metal of the contact plug from protruding into a second gate stack.

2. The integrated circuit structure of claim 1 , wherein the contact metal is W.

3. The integrated circuit structure of claim 1 , wherein the gate metal layer is a word line of a static random access memory (SRAM) cell.

4. The integrated circuit structure of claim 1 , wherein the work function layer has a thickness between about 10 Å to about 100 Å.

5. The integrated circuit structure of claim 1 , wherein the gate structure is part of an N-type field effect transistor (nFET).

6. The integrated circuit structure of claim 5 , wherein the work function layer is a P-type work function layer and is made of a material selected from a group consisting of TiN, WN, TaN, Re, Fe, Ru, Co, Rh, Ir, Ni, Pd, and Pt.

7. The integrated circuit structure of claim 1 , wherein the gate structure is part of a P-type field effect transistor (pFET).

8. The integrated circuit structure of claim 7 , wherein the work function layer is an N-type work function layer and is made of a material selected from a group consisting of TiAl, Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, and Zr.

9. The integrated circuit structure of claim 1 , wherein a minimum thickness of the work function layer is about 10 Å.

10. An integrated circuit structure comprising:

an N-type field effect transistor (nFET) gate structure with a first gate stack including a gate metal layer having a void; and

a contact plug filled with a contact metal, wherein the contact metal protrudes into the void and the contact plug is disposed directly on the gate metal layer of the first gate stack, and the gate metal layer underneath the contact plug is surrounded by the P-type work function layer to prevent the contact metal of the contact plug from protruding into a second gate stack of the integrated circuit structure, wherein the gate metal layer is a word line of a static random access memory (SRAM) cell.

11. An integrated circuit structure comprising:

a gate structure with a first gate stack including a gate metal layer having a void;

sidewalls formed surrounding the gate metal layer;

a contact plug filled with a contact metal wherein the contact metal protrudes into the void and the contact plug is disposed directly on the gate metal layer of the first gate stack; and

a work function layer, wherein the gate metal layer underneath the contact plug is surrounded by the work function layer to prevent the contact metal of the contact plug from protruding into a second gate stack of the integrated circuit structure.

12. The integrated circuit structure of claim 11 , wherein the work function layer has a thickness between about 10 Å to about 100 Å.

13. The integrated circuit structure of claim 11 , wherein the gate structure is part of an N-type field effect transistor (nFET).

14. The integrated circuit structure of claim 13 , wherein the work function layer is a P-type work function layer and comprises a material selected from a group consisting of TiN, WN, TaN, Re, Fe, Ru, Co, Rh, Ir, Ni, Pd, and Pt.

15. The integrated circuit structure of claim 11 , wherein the gate structure is part of a P-type field effect transistor (pFET).

16. The integrated circuit structure of claim 15 , wherein the work function layer is an N-type work function layer and comprises a material selected from a group consisting of TiAl, Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, and Zr.

17. The integrated circuit structure of claim 11 , further comprising:

an interface layer, wherein the work function layer is disposed between the interface layer and the metal gate layer.

18. The integrated circuit structure of claim 11 , further comprising:

an adhesion layer, wherein the adhesion layer is formed on an inner surface of the contact plug.

19. The integrated circuit structure of claim 18 , wherein the adhesion layer comprises at least one of Ti or TiN.

20. The integrated circuit structure of claim 11 , wherein the work function layer is disposed between the metal gate layer and the sidewalls.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 5, 2024
From: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
To: PARABELLUM STRATEGIC OPPORTUNITIES FUND LLC
Reel/Frame 068326/0474 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 10, 2010
From: TEO, LEE-WEE; ZHU, MING; LEE, CHI-JU; CHUNG, SHENG-CHEN; YOU, KAI-SHYANG; CHUANG, HARRY-HAK-LAY
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 024816/0543 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 26, 2010
From: TEO, LEE-WEE; ZHU, MING; LEE, CHI-JU; CHUNG, SHENG-CHEN; YOU, KAI-SHYANG; CHUANG, HARRY-HAK-LAY
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 023996/0459 →
Continuity (1)
Related Publication 20110210403A1 · Sep 1, 2011