Protection layer for adhesive material at wafer edge
View Patent ↗A wafer is attached to a carrier by using an adhesive layer, and a portion of the adhesive layer is exposed adjacent to an edge of the wafer. After thinning the wafer, a protection layer is provided to cover the exposed portion of the adhesive layer. A plurality of dies is bonded onto the thinned wafer, and then the thinned wafer and the dies are encapsulated with a molding compound.
1. A method, comprising:
providing a wafer having a first surface and a second surface opposite to the first surface;
attaching the first surface of the wafer to a carrier by using an adhesive layer, exposing a portion of the adhesive layer adjacent to an edge of the wafer;
thinning the wafer from the second surface, forming a thinned wafer;
forming a protection layer to cover the exposed portion of the adhesive layer;
bonding a plurality of dies onto the thinned wafer; and
encapsulating the thinned wafer and the plurality of dies with a molding compound.
2. The method of claim 1 , wherein the protection layer covers the edge of the wafer.
3. The method of claim 1 , wherein the protection layer covers a portion of the carrier adjacent to the edge of the wafer.
4. The method of claim 1 , wherein the protection layer covers at least a portion of the second surface of the wafer.
5. The method of claim 1 , wherein the protection layer comprises at least one of an oxide film, a nitride film, a carbide film, a dry film, a spin-on material film and combinations thereof.
6. The method of claim 1 , wherein the wafer comprises:
a semiconductor substrate having a front surface and a back surface;
a through via filled with a conductive material passing through at least a part of the semiconductor substrate; and
integrated circuits formed on the front surface of the semiconductor substrate.
7. The method of claim 6 , wherein after thinning the wafer, one end of the through via is exposed on the back surface of the semiconductor substrate.
8. The method of claim 6 , wherein the protection layer is formed on the back surface of the semiconductor substrate after thinning the wafer.
9. The method of claim 7 , further comprising forming a conductive structure on the exposed end of the through via before bonding the plurality of dies onto the thinned wafer.
10. The method of claim 9 , wherein the conductive structure comprises at least one of solder, copper, and a combination thereof.
11. The method of claim 9 , wherein the conductive structure comprises a redistribution layer (RDL).
12. A method, comprising:
providing a wafer having a first surface and a second surface opposite to the first surface;
attaching the first surface of the wafer to a carrier by using an adhesive layer, exposing a portion of the adhesive layer adjacent to an edge of the wafer;
thinning the wafer from the second surface, forming a thinned wafer;
forming a protection layer to cover the exposed portion of the adhesive layer, and the edge of the wafer;
bonding a die onto the thinned wafer;
encapsulating the thinned wafer and the die with a molding compound; and
removing the carrier.
13. The method of claim 12 , wherein the protection layer covers a portion of the carrier adjacent to the edge of the wafer.
14. The method of claim 12 , wherein the protection layer comprises at least one of an oxide film, a nitride film, a carbide film, a dry film, a spin-on material film or combinations thereof.
15. The method of claim 12 , wherein the wafer comprises:
a semiconductor substrate having a front surface and a back surface;
a through via filled with a conductive material passing through at least a part of the semiconductor substrate; and
integrated circuits formed on the front surface of the semiconductor substrate.
16. The method of claim 15 , wherein after thinning the wafer, one end of the through via is exposed on the back surface of the semiconductor substrate.
17. The method of claim 15 , wherein the protection layer is formed on the back surface of the semiconductor substrate after thinning the wafer.
18. The method of claim 17 , further comprising forming a conductive structure on the exposed end of the through via before bonding a plurality of the dies onto the thinned wafer.
19. The method of claim 18 , wherein the conductive structure comprises at least one of solder, copper or a combination thereof.
20. The method of claim 18 , wherein the conductive structure comprises a redistribution layer (RDL).