Method and structure for semiconductor device having gate spacer protection layer
A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and drain (S/D) contacts on opposing sides of the gate stack. The method further includes recessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack. The method further includes forming a spacer protection layer over the gate spacer, the first dielectric layer, and the S/D contacts.
1. A device comprising:
a first gate stack disposed over a substrate, the first gate stack including a gate electrode layer;
a first sidewall spacer disposed along a first sidewall of the first gate stack and a second sidewall spacer disposed along a second sidewall of the first gate stack, the second sidewall of the first gate stack being opposite the first sidewall of the first gate stack, the first sidewall spacer having a top surface facing away from the substrate, the gate electrode layer being recessed relative to the first sidewall spacer;
a first dielectric layer disposed between the first sidewall spacer and the second sidewall spacer, the first dielectric layer having a portion extending below the top surface of the first sidewall spacer;
a protection layer disposed along a sidewall of the first dielectric layer such that the protection layer physically contacts the sidewall of the first dielectric layer; and
a first contact extending through the protection layer and the first dielectric layer to the gate electrode layer such that the first contact physically contacts the protection layer, the first dielectric layer and the first sidewall spacer.
2. The device of claim 1 , wherein the protection layer is disposed directly on a top surface of the second sidewall spacer such that the protection layer physically contacts the top surface of the second sidewall spacer.
3. The device of claim 1 , wherein the first sidewall spacer and the second sidewall spacer extend to the same height above the substrate.
4. The device of claim 1 , wherein the protection layer includes an oxide material.
5. The device of claim 1 , wherein the protection layer includes a nitride material.
6. The device of claim 1 , wherein the protection layer and the first dielectric layer extend to the same height above the substrate.
7. The device of claim 1 , further comprising:
a source/drain associated with the first gate stack; and
a second contact extending to the source/drain, and
wherein the protection layer extends to the second contact.
8. The device of claim 1 , further comprising:
a second gate stack disposed over the substrate, the second gate stack including a second gate electrode layer; and
a third sidewall spacer disposed along a third sidewall of the second gate stack, and
wherein the protection layer physically contacts the third sidewall spacer.
9. The device of claim 8 , further comprising:
a fourth sidewall spacer disposed along a fourth sidewall of the second gate stack, the fourth sidewall of the second gate stack being opposite the third sidewall of the second gate stack such that a second recess is formed between the third and fourth sidewall spacers;
a second dielectric layer disposed within the second recess between the third sidewall spacer and the fourth sidewall spacer.
10. The device of claim 9 , wherein the protection layer further extends to the second dielectric layer.
11. The device of claim 9 , further comprising a second contact extending through the protection layer and the second dielectric layer to the second gate electrode layer.
12. A device comprising:
a gate stack disposed over a substrate, the gate stack including a gate electrode layer;
a first sidewall spacer disposed along a first sidewall of the gate stack, the gate electrode layer being recessed relative to the first sidewall spacer;
a first dielectric layer disposed over the gate electrode layer, the first dielectric layer having a portion extending below a top surface of the first sidewall spacer;
a spacer protection layer disposed over the first sidewall spacer and interfacing with the first dielectric layer; and
a first contact extending through the first dielectric layer and the spacer protection layer such that the first contact interfaces with the first dielectric layer and the spacer protection layer.
13. The device of claim 12 , wherein the first dielectric layer includes a nitride material.
14. The device of claim 12 , wherein the spacer protection layer interfaces with the first sidewall spacer.
15. The device of claim 12 , wherein the spacer protection layer and the first dielectric layer extend to the same height above the substrate.
16. The device of claim 12 , further comprising:
a source/drain associated with the gate stack; and
a second contact electrically coupled to the source/drain, and
wherein the spacer protection layer interfaces with the second contact.
17. A device comprising:
a first gate stack disposed over a substrate, the first gate stack including a gate electrode layer;
a first sidewall spacer disposed along a first sidewall of the first gate stack and a second sidewall spacer disposed along a second sidewall of the first gate stack, the second sidewall of the first gate stack being opposite the first sidewall of the first gate stack, the first sidewall spacer having a top surface facing away from the substrate, the gate electrode layer being recessed relative to the first sidewall spacer;
a first dielectric layer disposed between the first sidewall spacer and the second sidewall spacer, the first dielectric layer having a portion extending below the top surface of the first sidewall spacer;
a protection layer disposed over the first gate stack and physically contacting the first dielectric layer; and
a first contact extending through the protection layer and the first dielectric layer to the gate electrode layer such that the first contact physically contacts the protection layer, the first dielectric layer and the first sidewall spacer.
18. The device of claim 17 , wherein the protection layer includes a material selected from the group consisting of a metal nitride material and a metal oxide material.
19. The device of claim 17 , wherein the protection layer physically contacts the second sidewall spacer.
20. The device of claim 19 , further comprising a contact etch stop layer disposed on and physically contacting the protection layer, the first contact, and the first dielectric layer.